# US 10,372,659 B2 · Multi-mode NMVE over fabrics devices

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- Number: US 10,372,659 B2
- Document ID: US10372659B2
- Status: Granted
- Kind: B2
- Application number: 15/411,962
- Filed: 2017-01-20
- Published: 2018-02-01
- Granted: 2019-08-06
- Earliest claimed: 2016-07-26
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sompong Paul Olarig; Son T. Pham; Fred Worley
- Web page: https://patentgrep.com/patent/US10372659B2

## CPC

- G06F 13/4234: {being a memory bus}
- G06F 3/0601: {Interfaces specially adapted for storage systems}
- G06F 13/387: {for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 2213/0026: PCI express
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A device may include a connector to connect the device to a chassis. The device may include chassis type circuitry to determine a type of the chassis. The device may further include mode configuration circuitry to configure the device to use a particular mode appropriate for the type of the chassis.

## Claims

### Claim 1

A storage device, comprising:
a connector to connect the storage device to a chassis, the connector supporting a plurality of Peripheral Component Interconnect Express (PCIe) lanes and Serial Attached Small Computer System Interface (SCSI) (SAS) pins;
chassis type circuitry to determine a type of the chassis including the storage device; and
mode configuration circuitry to configure the storage device to use a first mode or a second mode responsive to the type of the chassis,
wherein the first mode includes a Non-Volatile Memory Express (NVMe) protocol to communicate between the storage device and the chassis, and
wherein the second mode includes a Non-Volatile Memory Express over Fabric (NVMeoF) protocol to communicate between the storage device and the chassis.

### Claim 2 (depends on 1)

The storage device according to claim 1, wherein the chassis type circuitry is operative to determine the type of the chassis from a signal on a pin on the connector.

### Claim 3 (depends on 1)

The storage device according to claim 1, wherein the connector includes a U.2 connector.

### Claim 4 (depends on 1)

The storage device according to claim 1, wherein, based at least in part on the type of the chassis being NVMe, the mode configuration circuitry is operative to use a first two lanes of the PCIe lanes as both a first data plane and a first control plane for a first host and to disable use of an Ethernet port via the SAS pins.

### Claim 5 (depends on 1)

The storage device according to claim 1, wherein, based at least in part on the type of the chassis being NVMeoF, the mode configuration circuitry is operative to use a first two lanes of the PCIe lanes as a first control plane for a first host, and to use a first set of SAS pins as a first Ethernet port for a first data plane.

### Claim 6 (depends on 1)

The storage device according to claim 1, wherein the chassis type circuitry is operative to determine whether the type of the chassis is a High Availability (HA) chassis.

### Claim 7 (depends on 6)

The storage device according to claim 6, wherein, based at least in part on the type of the chassis being NVMe, the mode configuration circuitry is operative to use a second two lanes of the PCIe lanes as both a second data plane and a second control plane for a second host and to disable use of an Ethernet port via the SAS pins.

### Claim 8 (depends on 6)

The storage device according to claim 6, wherein, based at least in part on the type of the chassis being NVMeoF, the mode configuration circuitry is operative to use a second two lanes of the PCIe lanes as a second control plane for a second host, and to use a second set of SAS pins as a second Ethernet port for a second data plane.

### Claim 9

A method, comprising:
determining a type of chassis in which a storage device is installed, including determining whether the type of chassis is a Non-Volatile Memory Express (NVMe) chassis or a Non-Volatile Memory Express over Fabrics (NVMeoF) chassis; and
configuring the storage device to enable a first communication mechanism and disable a second communication mechanism for the storage device according to the type of the chassis,
wherein the storage device is coupled to the chassis using a connector supporting a plurality of Peripheral Component Interconnect Express (PCIe) lanes and Serial Attached Small Computer System Interface (SCSI) (SAS) pins.

### Claim 10 (depends on 9)

The method according to claim 9, wherein determining a type of chassis in which a storage device is installed includes accessing a signal from a pin on the connector.

### Claim 11 (depends on 9)

The method according to claim 9, wherein configuring the storage device to enable a first communication mechanism and disable a second communication mechanism for the storage device according to the type of the chassis includes, based at least in part on the type of the chassis being the NVMe chassis:
enabling the storage device to use two lanes in a Peripheral Component Interconnect Express (PCIe) bus as both a first data plane and a first control plane for a first host; and
disabling the storage device from using an Ethernet port on the storage device for the first host.

### Claim 12 (depends on 11)

The method according to claim 11, wherein:
determining a type of chassis in which a storage device is installed further includes determining whether the type of the chassis is a High Availability (HA) chassis; and
the method further comprises determining whether the storage device is a HA storage device.

### Claim 13 (depends on 12)

The method according to claim 12, wherein, configuring the storage device to enable a first communication mechanism and disable a second communication mechanism for the storage device according to the type of the chassis includes, based at least in part on the type of the chassis being a HA chassis and the storage device being a HA storage device:
enabling a second two lanes in a Peripheral Component Interconnect Express (PCIe) bus as both a second data plane and a second control plane for a second host.

### Claim 14 (depends on 9)

The method according to claim 9, wherein configuring the storage device to enable a first communication mechanism and disable a second communication mechanism for the storage device according to the type of the chassis includes, based at least in part on the type of the chassis being the NVMeoF chassis:
enabling a first two lanes in a Peripheral Component Interconnect Express (PCIe) bus as a first control plane for a first host;
enabling a first Ethernet port on the storage device as a first data plane for the first host using a first pair of SAS pins on a connector coupled to the storage device as the first Ethernet port; and
disabling the lanes in the PCIe bus as the first data plane for the first host.

### Claim 15 (depends on 14)

The method according to claim 14, wherein:
determining a type of chassis in which a storage device is installed further includes determining whether the type of the chassis is a High Availability (HA) chassis; and
the method further comprises determining whether the storage device is a HA storage device.

### Claim 16 (depends on 15)

The method according to claim 15, wherein, configuring the storage device to enable a first communication mechanism and disable a second communication mechanism for the storage device according to the type of the chassis includes, based at least in part on the type of the chassis being a HA chassis and the storage device being a HA storage device:
enabling a second two lanes in a Peripheral Component Interconnect Express (PCIe) bus as a second control plane for a second host; and
enabling a second Ethernet port on the storage device as a second data plane for the second host.

### Claim 17 (depends on 16)

The method according to claim 16, wherein enabling a second Ethernet port on the storage device as a second data plane for the second host includes using a second pair of SAS pins on the connector coupled to the storage device as the second Ethernet port.

### Claim 18

An article, comprising a tangible non-transitory storage medium, the tangible non-transitory storage medium having stored thereon non-transitory instructions that, when executed by a machine, result in:
determining a type of chassis in which a storage device is installed, including determining whether the type of chassis is a Non-Volatile Memory Express (NVMe) chassis or a Non-Volatile Memory Express over Fabrics (NVMeoF) chassis; and
configuring the storage device to enable a first communication mechanism and disable a second communication mechanism for the storage device according to the type of the chassis,
wherein the storage device is coupled to the chassis using a connector supporting a plurality of Peripheral Component Interconnect Express (PCIe) lanes and Serial Attached Small Computer System Interface (SCSI) (SAS) pins.
