# US 10,372,653 B2 · Apparatuses for providing data received by a state machine engine > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,653 B2 - Document ID: US10372653B2 - Status: Granted - Kind: B2 - Application number: 16/053,562 - Filed: 2018-08-02 - Published: 2018-11-29 - Granted: 2019-08-06 - Earliest claimed: 2013-03-15 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: David R. Brown; Harold B Noyes; Inderjit S. Bains - Web page: https://patentgrep.com/patent/US10372653B2 ## CPC - G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)} - G06F 9/4498: {Finite state machines} - G06F 15/7867: {with reconfigurable architecture} - G06N 3/08: Learning methods - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines. ## Claims ### Claim 1 A system comprising: a processor; and a rank of state machine engines, wherein the state machine engines of the rank are coupled together by an inter-rank bus, and wherein the rank of state machines can be configured as one logical group, and wherein the rank of state machines also can be configured as multiple logical groups, wherein the inter-rank bus enables each state machine engine of the rank to receive an assigned portion of a data stream to be analyzed when the rank is configured as multiple logical groups. ### Claim 2 A system comprising: a processor; and a rank of state machine engines, wherein the state machine engines of the rank are coupled together by an inter-rank bus, and wherein the rank of state machines can be configured as one logical group, and wherein the rank of state machines also can be configured as multiple logical groups, wherein the processor is configured to assign a number to each state machine engine of the rank, wherein the rank of state machine engines comprises a module including the rank, and wherein the processor is configured to assign the number during initialization of the module. ### Claim 3 A system comprising: a processor; and a rank of state machine engines, wherein the state machine engines of the rank are coupled together by an inter-rank bus, and wherein the rank of state machines can be configured as one logical group, and wherein the rank of state machines also can be configured as multiple logical groups, wherein the processor is configured to provide data to a particular state machine engine of the rank to configure the particular state machine engine as a master device. ### Claim 4 (depends on 3) The system of claim 3, wherein the master device is configured to coordinate synchronization of the state machine engines of the rank. ### Claim 5 (depends on 1) The system of claim 1, wherein the processor is configured to provide data to each state machine engine of the rank to indicate a total number of state machine engines that are part of the rank. ### Claim 6 (depends on 1) The system of claim 1, wherein the processor is configured to provide data to each state machine engine of the rank to indicate a logical group to which the respective state machine engine belongs. ### Claim 7 (depends on 1) The system of claim 1, wherein the processor is configured to provide data to each state machine engine of the rank to indicate a number of logical groups that are part of the rank. ### Claim 8 (depends on 1) The system of claim 1, wherein the inter-rank bus enables each state machine engine of the rank to analyze all bytes of data collectively received for analysis by the state machine engines of the rank when the rank is configured as one logical group. ### Claim 9 (depends on 8) The system of claim 8, wherein each of the state machine engines of the rank is configured to process an entire data stream received for analysis by the rank. ### Claim 10 (depends on 1) The system of claim 1, wherein the system implements a data-slicing scheme to assign the portions of the data stream to the state machine engines. ### Claim 11 (depends on 1) The system of claim 1, wherein the processor is configured to sequentially provide data intended for each logical group of the multiple logical groups and wherein the state machine engines of the rank store the data in an offset manner. ### Claim 12 (depends on 1) The system of claim 1, wherein the state machine engines of the rank are coupled to data lines of the processor. ### Claim 13 (depends on 1) The system of claim 1, wherein the inter-rank bus is configured to allow data to be exchanged between the state machine engines of the rank. ### Claim 14 A system comprising: a processor; and a rank of state machine engines configured as one logical group, wherein the state machine engines of the rank are coupled together by an inter-rank bus, each state machine engine of the rank being configured to: store a respective portion of data received at an interface; provide the respective portion of data to the inter-rank bus in a data burst; and analyze all of the portions of data provided to the inter-rank bus by the state machine engines of the rank during the data burst. ### Claim 15 (depends on 14) The system of claim 14, wherein each state machine engine of the rank includes a data buffer to store the respective portion of data and a process buffer to store all of the portions of data provided to the inter-rank bus during the data burst. ### Claim 16 A system comprising: a processor; and a rank of state machine engines configured as multiple logical groups, wherein the state machine engines of the rank are coupled together by an inter-rank bus, each state machine engine of the rank being configured to: store respective portions of data received at an interface; provide the respective portions of data to the inter-rank bus in a data burst; and analyze portions of data provided on the inter-rank bus that correspond to the logical group to which the respective state machine engine belongs. ### Claim 17 (depends on 16) The system of claim 16, wherein the processor is configured to sequentially provide data intended for each logical group of the multiple logical groups and wherein the state machine engines of the rank are configured to store the provided data in an offset manner. ### Claim 18 (depends on 16) The system of claim 16, wherein at least one of the multiple logical groups includes a different number of state machine engines than another one of the multiple logical groups. ### Claim 19 (depends on 16) The system of claim 16, wherein the rank of state machine engines is configured to store the data in an offset manner among the state machine engines of the rank. ### Claim 20 (depends on 16) The system of claim 16, wherein each state machine engine of the rank includes a data buffer to store the respective portions of data and a process buffer to store the portions of data that correspond to the logical group to which the respective state machine engine belongs. ### Claim 21 (depends on 14) The system of claim 14, wherein the respective portion of data comprises a respective byte of data. ### Claim 22 (depends on 16) The system of claim 16, wherein the respective portions of data comprise respective bytes of data.