# US 10,372,646 B2 · Programmable adapter between slow peripherals and network on-chip interfaces > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,646 B2 - Document ID: US10372646B2 - Status: Granted - Kind: B2 - Application number: 15/639,832 - Filed: 2017-06-30 - Published: 2019-01-03 - Granted: 2019-08-06 - Earliest claimed: 2017-06-30 - Assignees: Western Digital Technologies, Inc. - Applicants: Western Digital Technologies, Inc. - Inventors: James V. Henson - Web page: https://patentgrep.com/patent/US10372646B2 ## CPC - G06F 13/387: {for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system} - G06F 13/124: {where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine} - G06F 13/24: using interrupt (G06F13/32 takes precedence) - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F 13/404: {with address mapping} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 15/7825: {Globally asynchronous, locally synchronous, e.g. network on chip} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method and system for adapting communication between a low-speed interface and a high-speed interface is disclosed. The method includes retrieving configuration instructions in response to a power-up of a microcontroller, where the configuration instructions associated with a low-speed communication protocol. The method includes sending the configuration instructions to a low-speed interface module causing the low-speed interface module to configure an interface of the low-speed interface module based on the configuration instructions. The method includes receiving, by the interface of the low-speed interface module, data associated with the low-speed communication protocol. The method includes retrieving, by the microcontroller, mapping instructions associated with a high-speed communication protocol. The method also includes sending, by the microcontroller, the mapping instructions to the low-speed interface module, causing the low-speed interface module to convert the data associated with the low-speed communication protocol to data associated with the high-speed communication protocol. ## Claims ### Claim 1 A method for adapting communication between a low-speed interface and a high-speed interface, the method comprising: retrieving, by a microcontroller and via a memory bus, configuration instructions in response to a power-up of the microcontroller, the configuration instructions associated with a low-speed communication protocol; sending, by the microcontroller and via an address/data bus, the configuration instructions to a low-speed interface module causing the low-speed interface module to configure an interface of the low-speed interface module based on the configuration instructions; entering, by the microcontroller, a low-power mode; receiving, by the interface of the low-speed interface module, data associated with the low-speed communication protocol; changing, by the low-speed interface module and in response to receiving the data, a state of an interrupt signal causing the microcontroller to wake from the low-power mode; retrieving, by the microcontroller via an instruction bus, mapping instructions associated with a high-speed communication protocol; and sending, by the microcontroller and via the address/data bus, the mapping instructions to the low-speed interface module, causing the low-speed interface module to convert the data associated with the low-speed communication protocol to data associated with the high-speed communication protocol. ### Claim 2 (depends on 1) The method of claim 1, wherein retrieving configuration instructions comprises: receiving, by the microcontroller and via the address/data bus, a request for the configuration instructions from the low-speed interface module, the request comprising the low-speed communication protocol. ### Claim 3 (depends on 1) The method of claim 1, wherein retrieving configuration instructions comprises: executing, by the microcontroller and via the instruction bus, instructions stored at an initial address of an instruction memory, the instruction memory separate from the microcontroller and dedicated to the microcontroller. ### Claim 4 (depends on 1) The method of claim 1, wherein the address/data bus is separate from the instruction bus, the address/data bus is separate from the memory bus, and the memory bus is separate from the instruction bus. ### Claim 5 (depends on 1) The method of claim 1, wherein entering the low-power mode comprises: executing, by the microcontroller and via the instruction bus, a wait for interrupt (WFI) instruction stored at a first address of an instruction memory, the instruction memory separate from the microcontroller and dedicated to the microcontroller. ### Claim 6 (depends on 5) The method of claim 5, wherein retrieving mapping instructions associated with the high-speed communication protocol comprises: executing, by the microcontroller and via the instruction bus, a jump to subroutine (JSR) instruction stored at a second address of the instruction memory, causing the microcontroller to execute a subroutine stored at a third address of the instruction memory, the third address stored after the second address. ### Claim 7 (depends on 1) The method of claim 1, the method further comprising: receiving, by the microcontroller and via the address/data bus, a request for new configuration instructions from the low-speed interface module, the request for new configuration instructions comprising a new low-speed communication protocol, the low-speed communication protocol different than the new low-speed communication protocol. ### Claim 8 (depends on 1) The method of claim 1, the method further comprising: sending, by the microcontroller and via the address/data bus, new mapping instructions to the low-speed interface module causing the low-speed interface module to convert the data associated with the low-speed communication protocol to data associated with a new high-speed communication protocol, the high-speed communication protocol different than the new high-speed communication protocol. ### Claim 9 (depends on 1) The method of claim 1, the method further comprising: receiving, by an interface of a high-speed interface module, data associated with the high-speed communication protocol; and sending, by the microcontroller and via the address/data bus, new mapping instructions to the high-speed interface module causing the high-speed interface module to convert the data associated with the high-speed communication protocol to data associated with the low-speed communication protocol. ### Claim 10 (depends on 1) The method of claim 1: wherein the low-speed communication protocol comprises at least one of Advanced Microcontroller Bus Architecture (AMBA) Advanced System Bus (ASB), AMBA Advanced Peripheral Bus (APB), AMBA High-Performance Bus (HPB), and AMBA AXI industry standard interfaces; wherein the high-speed communication protocol comprises at least one of AMBA ASB, AMBA APB, AMBA HPB, and AMBA AXI industry standard interfaces; and wherein a data rate of the low-speed communication protocol is lower than a data rate of the high-speed communication protocol. ### Claim 11 An interface adapter for adapting communication between a low-speed interface and a high- speed interface, the interface adapter comprising: a microcontroller comprising a first input terminal, a second input terminal, a first bidirectional terminal, a second bidirectional terminal, and a third bidirectional terminal; a high-speed interface module comprising an output terminal, a first bidirectional terminal, a second bidirectional terminal, and a third bidirectional terminal, wherein the output terminal couples to the second input terminal of the microcontroller; a low-speed interface module comprising an output terminal coupled to the first input terminal of the microcontroller, a first bi-directional terminal, a second bidirectional terminal coupled to the third bidirectional terminal of the microcontroller and the second bidirectional terminal of the high-speed interface module, and a third bidirectional terminal coupled to the third bidirectional terminal of the high-speed interface module; and an instruction memory comprising a bidirectional output terminal coupled to the second bidirectional terminal of the microcontroller. ### Claim 12 (depends on 11) The interface adapter of claim 11, further comprising a memory comprising a bidirectional terminal coupled to the first bidirectional terminal of the microcontroller. ### Claim 13 (depends on 11) The interface adapter of claim 11, wherein the microcontroller is adapted to send, via the third bidirectional terminal of the microcontroller, configuration instructions associated with a low-speed communication protocol to the low-speed interface module causing the low-speed interface module to configure an interface associated with the first bidirectional terminal of the low-speed interface module based on the configuration instructions. ### Claim 14 (depends on 13) The interface adapter of claim 13, wherein the low-speed interface module is adapted to change, in response to receiving data on the interface that is associated with a low-speed communication protocol, a state of an interrupt signal causing the microcontroller to wake from a low-power mode. ### Claim 15 (depends on 14) The interface adapter of claim 14, wherein the microcontroller is further adapted to: retrieve, via the first bidirectional terminal of the microcontroller, mapping instructions associated with a high-speed communication protocol; and send, via the third bidirectional terminal of the microcontroller, the mapping instructions to the low-speed interface module, causing the low-speed interface module to convert the data associated with the low-speed communication protocol to data associated with the high-speed communication protocol. ### Claim 16 (depends on 15) The interface adapter of claim 15, wherein the microcontroller is further adapted to: execute, via the second bidirectional terminal of the microcontroller, a jump to subroutine (JSR) instruction stored at a first address of the instruction memory, causing the microcontroller to execute a subroutine stored at a second address of the instruction memory, wherein the second address stored after the first address, wherein the subroutine causes the microcontroller to retrieve mapping instructions associated with the high-speed communication protocol. ### Claim 17 (depends on 15) The interface adapter of claim 15, wherein the high-speed interface module is adapted to receive data associated with the high-speed communication protocol. ### Claim 18 (depends on 17) The interface adapter of claim 17, wherein the microcontroller is further adapted to: send, via the third bidirectional terminal of the microcontroller, new mapping instructions to the high-speed interface module causing the high-speed interface module to convert the data associated with the high-speed communication protocol to data associated with the low-speed communication protocol. ### Claim 19 (depends on 17) The interface adapter of claim 17: wherein the low-speed communication protocol comprises at least one of Advanced Microcontroller Bus Architecture (AMBA) Advanced System Bus (ASB), AMBA Advanced Peripheral Bus (APB), AMBA High-Performance Bus (HPB), and AMBA AXI industry standard interfaces; wherein the high-speed communication protocol comprises at least one of AMBA ASB, AMBA APB, AMBA HPB, and AMBA AXI industry standard interfaces; and wherein a data rate of the low-speed communication protocol is lower than a data rate of the high-speed communication protocol. ### Claim 20 (depends on 17) The interface adapter of claim 17, wherein the microcontroller is further adapted to: enter the low-power mode by executing, via the second bidirectional terminal of the microcontroller, a wait for interrupt (WFI) instruction stored at a first address of the instruction memory, the instruction memory separate from the microcontroller and dedicated to the microcontroller. ### Claim 21 A non-transitory computer readable storage medium to store a computer program configured to execute a method for adapting communication between a low-speed interface and a high-speed interface, the method comprising: retrieving, by a microcontroller and via a memory bus, configuration instructions in response to a power-up of the microcontroller, the configuration instructions associated with a low-speed communication protocol; sending, by the microcontroller and via an address/data bus, the configuration instructions to a low-speed interface module causing the low-speed interface module to configure an interface of the low-speed interface module based on the configuration instructions; entering, by the microcontroller, a low-power mode; receiving, by the interface of the low-speed interface module, data associated with the low-speed communication protocol; changing, by the low-speed interface module and in response to receiving the data, a state of an interrupt signal causing the microcontroller to wake from the low-power mode; retrieving, by the microcontroller via an instruction bus, mapping instructions associated with a high-speed communication protocol; and sending, by the microcontroller and via the address/data bus, the mapping instructions to the low-speed interface module, causing the low-speed interface module to convert the data associated with the low-speed communication protocol to data associated with the high-speed communication protocol. ### Claim 22 (depends on 21) The non-transitory computer readable storage medium of claim 21, the method further comprising: receiving, by an interface of a high-speed interface module, data associated with the high-speed communication protocol; and sending, by the microcontroller and via the address/data bus, new mapping instructions to the high-speed interface module causing the high-speed interface module to convert the data associated with the high-speed communication protocol to data associated with the low-speed communication protocol. ### Claim 23 An interface adapter for adapting communication between two interfaces, the interface adapter comprising: a microcontroller comprising a first input terminal, a second input terminal, a first bidirectional terminal, a second bidirectional terminal, and a third bidirectional terminal; a transmitting interface module comprising an output terminal, a first bidirectional terminal, a second bidirectional terminal, and a third bidirectional terminal, wherein the output terminal couples to the second input terminal of the microcontroller; a receiving interface module comprising an output terminal coupled to the first input terminal of the microcontroller, a first bi-directional terminal, a second bidirectional terminal coupled to the third bidirectional terminal of the microcontroller and the second bidirectional terminal of the transmitting interface module, and a third bidirectional terminal coupled to the third bidirectional terminal of the transmitting interface module; and an instruction memory comprising a bidirectional output terminal coupled to the second bidirectional terminal of the microcontroller. ### Claim 24 (depends on 23) The interface adapter of claim 23: wherein the transmitting interface module is associated with a low-speed communication protocol and the receiving interface module is associated with a high-speed communication protocol; wherein the low-speed communication protocol comprises at least one of Advanced Microcontroller Bus Architecture (AMBA) Advanced System Bus (ASB), AMBA Advanced Peripheral Bus (APB), AMBA High-Performance Bus (HPB), and AMBA AXI industry standard interfaces; wherein the high-speed communication protocol comprises at least one of AMBA ASB, AMBA APB, AMBA HPB, and AMBA AXI industry standard interfaces; and wherein a data rate of the low-speed communication protocol is lower than a data rate of the high-speed communication protocol.