# US 10,372,635 B2 · Dynamically determining memory attributes in processor-based systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,635 B2 - Document ID: US10372635B2 - Status: Granted - Kind: B2 - Application number: 15/637,290 - Filed: 2017-06-29 - Published: 2018-03-01 - Granted: 2019-08-06 - Earliest claimed: 2016-08-26 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Thomas Philip Speier - Web page: https://patentgrep.com/patent/US10372635B2 ## CPC - G06F 13/161: {with latency improvement} - G06F 3/061: {Improving I/O performance} - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 9/5016: {the resource being the memory} - G06F 12/0223: {User address space allocation, e.g. contiguous or non contiguous base addressing} - G06F 12/023: {Free address space management} - G06F 12/06: Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) - G06F 12/0638: {Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70)} - G06F 13/1673: {using buffers} - G06F 12/0804: with main memory updating (G06F12/0806 takes precedence) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Providing dynamic determination of memory attributes in processor-based systems is disclosed. In this regard, in some aspects, a processor-based system comprises a processor device and one or more memory devices, each of which is associated with one of a plurality of memory attributes. The processor device transmits a request to one of the memory devices to determine the memory attribute associated with the memory device. In response to the request, the memory device provides a memory attribute indication that informs the processor device of the memory attribute associated with the memory device. The processor device in some aspects then performs subsequent memory access operations on the memory device based on the memory attribute indication. Some aspects may provide that the processor device also stores the memory attribute indication, and performs subsequent memory access operations based on the stored memory attribute indication. ## Claims ### Claim 1 A processor-based system for providing dynamic determination of memory attributes, comprising: a processor device; and one or more memory devices each associated with a memory attribute of a plurality of memory attributes; the processor device configured to: transmit a request to a memory device of the one or more memory devices to determine a memory attribute of the memory device; receive, from the memory device, a memory attribute indication indicating the memory attribute of the memory device, wherein the memory attribute comprises an architectural memory type indicating one of a normal memory and a device memory; and perform a subsequent memory access operation on the memory device based on the memory attribute indication received from the memory device, wherein the processor device is configured to perform the subsequent memory access operation by being configured to: determine, based on the memory attribute indication, whether the memory comprises normal memory; and responsive to determining that the memory comprises normal memory, enable one or more of a speculative read operation and a cache operation on the memory. ### Claim 2 (depends on 1) The processor-based system of claim 1, wherein the processor device is configured to transmit the request by being configured to transmit a memory attribute query indicating a request that the memory attribute of the memory device be provided. ### Claim 3 (depends on 1) The processor-based system of claim 1, wherein the processor device is configured to: transmit the request by being configured to transmit a first memory access request to the memory device; and receive the memory attribute indication by being configured to receive a memory access response comprising the memory attribute indication. ### Claim 4 (depends on 1) The processor-based system of claim 1, wherein the memory attribute further comprises one of a memory persistence type, a memory attachment type, and a memory latency. ### Claim 5 (depends on 1) The processor-based system of claim 1, wherein the memory attribute indication comprises one or more of a size of a memory region associated with the memory attribute, a start address and an end address of a memory region associated with the memory attribute, and a mask indicating memory addresses associated with the memory attribute. ### Claim 6 (depends on 1) The processor-based system of claim 1, wherein the processor device is further configured to: store the memory attribute indication in an internal data structure; and perform a subsequent memory access operation based on the memory attribute indication stored in the internal data structure. ### Claim 7 (depends on 6) The processor-based system of claim 6, wherein the processor device is configured to store the memory attribute indication in the internal data structure by being configured to store the memory attribute indication in one of a translation lookaside buffer (TLB), a page table, a register, and a memory lookup table. ### Claim 8 (depends on 1) The processor-based system of claim 1 integrated into an integrated circuit (IC). ### Claim 9 (depends on 1) The processor-based system of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter. ### Claim 10 A method for providing dynamic determination of memory attributes, comprising: transmitting, by a processor device of a processor-based system, a request to a memory device of one or more memory devices of the processor-based system to determine a memory attribute of the memory device; providing, by the memory device, a memory attribute indication indicating the memory attribute of the memory device to the processor device, wherein the memory attribute comprises an architectural memory type indicating one of a normal memory and a device memory; and performing a subsequent memory access operation on the memory device based on the memory attribute indication received from the memory device, wherein performing the subsequent memory access operation comprises: determining, based on the memory attribute indication, whether the memory comprises normal memory; and responsive to determining that the memory comprises normal memory, enabling one or more of a speculative read operation and a cache operation on the memory. ### Claim 11 (depends on 10) The method of claim 10, wherein the request comprises a memory attribute query indicating a request that the memory attribute of the memory device be provided. ### Claim 12 (depends on 10) The method of claim 10, wherein: the request comprises a first memory access request to the memory device; and providing the memory attribute indication comprises providing a memory access response comprising the memory attribute indication. ### Claim 13 (depends on 10) The method of claim 10, wherein the memory attribute further comprises one of a memory persistence type, a memory attachment type, and a memory latency. ### Claim 14 (depends on 10) The method of claim 10, wherein the memory attribute indication comprises one or more of a size of a memory region associated with the memory attribute, a start address and an end address of a memory region associated with the memory attribute, and a mask indicating interleaved memory addresses associated with the memory attribute. ### Claim 15 (depends on 10) The method of claim 10, further comprising: storing, by the processor device, the memory attribute indication in an internal data structure; and performing, by the processor device, a subsequent memory access operation based on the memory attribute indication stored in the internal data structure. ### Claim 16 (depends on 15) The method of claim 15, wherein the internal data structure comprises one of a translation lookaside buffer (TLB), a page table, a register, and a memory lookup table.