# US 10,372,622 B2 · Software controlled cache line replacement within a data property dependent cache segment of a cache using a cache segmentation enablement bit and cache segment selection bits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,622 B2 - Document ID: US10372622B2 - Status: Granted - Kind: B2 - Application number: 15/417,302 - Filed: 2017-01-27 - Published: 2018-08-02 - Granted: 2019-08-06 - Earliest claimed: 2017-01-27 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Shajith Chandran - Web page: https://patentgrep.com/patent/US10372622B2 ## CPC - G06F 12/109: for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) - G06F 12/0893: Caches characterised by their organisation or structure - G06F 12/1009: using page tables, e.g. page table structures - G06F 12/12: Replacement control - G06F 12/127: using additional replacement algorithms - G06F 12/0848: {Partitioned cache, e.g. separate instruction and operand caches} - G06F 2212/1056: Simplification - G06F 2212/657: Virtual address space management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Mechanisms are provided, in a data processing system having a processor and a cache subsystem, for providing software controlled cache segmentation and cache segment utilization. The mechanisms segment a cache memory of the cache subsystem such that the cache memory comprises a plurality of cache segments. Each cache segment in the plurality of cache segments is associated with a different data property of data stored in the cache segment. The mechanisms configure software executing on the data processing system to direct cache accesses to one of the cache segments based on a corresponding data property of the cache accesses by the software. The mechanisms process, by the processor, a data access operation from software executing on the processor, based on an identifier of a cache segment in one of an effective address provided by the software or a page table entry corresponding to the effective address provided by the software. ## Claims ### Claim 1 A method, in a data processing system having a processor and a cache subsystem, comprising: segmenting a cache memory of the cache subsystem such that the cache memory comprises a plurality of cache segments, wherein each cache segment in the plurality of cache segments is associated with a different data property of data stored in the cache segment; configuring software executing on the data processing system to direct cache accesses to one of the cache segments based on a corresponding data property of the cache accesses by the software; and processing, by the processor, a data access operation from the software executing on the processor, based on an identifier of a cache segment in one of an effective address provided by the software or a page table entry corresponding to the effective address provided by the software, wherein the identifier comprises a cache segmentation enablement bit that indicates cache segmenting is used with a page frame corresponding to the page table entry and one or more cache segment selection bits that each indicate a cache segment to be used for caching the cache lines from the page frame corresponding to the page table entry. ### Claim 2 (depends on 1) The method of claim 1, wherein the software is one of an application, an operating system, or a virtual machine monitor. ### Claim 3 (depends on 1) The method of claim 1, wherein the identifier of the cache segment is in the page table entry in a hardware page table. ### Claim 4 (depends on 3) The method of claim 3, wherein the one or more cache segment selection bits identify a specific cache segment in which data, corresponding to a page frame of a page corresponding to the page table entry, is stored. ### Claim 5 (depends on 1) The method of claim 1, wherein the identifier of the cache segment is a cache segment selection bit of the one or more cache section selection bits in the effective address. ### Claim 6 (depends on 5) The method of claim 5, wherein segmenting the cache comprises mapping a first range of effective addresses to a first cache segment and associating a first cache segment selection bit setting in effective addresses with the first cache segment, and mapping a second range of effective addresses to a second cache segment and associating a second cache segment selection bit setting in effective address with the second cache segment. ### Claim 7 (depends on 1) The method of claim 1, wherein the software executing on the processor controls, via operating system calls, mapping of data utilized by the software to a particular cache segment or set of cache segments at a page level via a page table entry cache segment enable/disable bit and at least one page table entry cache segment selection bit in the page table entry in a hardware page table. ### Claim 8 (depends on 1) The method of claim 1, wherein data property of the data comprises a data longevity property that specifies whether corresponding data is to be placed in a long term data cache segment or a short term data cache segment of the cache, and wherein the identifier of a cache segment identifies one of the long term data cache segment or the short term data cache segment of the cache. ### Claim 9 (depends on 1) The method of claim 1, wherein an operating system executing in the data processing system restricts a relatively low priority process of the software executing on the processor to a particular cache segment or set of cache segments by setting cache segment enable/disable bits and cache segment selection bits in page table entries of all page frames used by the relatively low priority process to point to a same cache segment. ### Claim 10 (depends on 1) The method of claim 1, wherein a virtual machine monitor (VMM) executing in the data processing system restricts a logical partition (LPAR) or virtual machine executing in the data processing system to a particular cache segment or set of cache segments, by setting cache segment enable/disable bits and cache segment selection bits in page table entries of all page frames used by the LPAR or virtual machine to point to a same cache segment. ### Claim 11 A computer program product comprising a non-transitory computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device comprising a processor and a cache subsystem comprising a cache memory, causes the computing device to; segment the cache memory of the cache subsystem such that the cache memory comprises a plurality of cache segments, wherein each cache segment in the plurality of cache segments is associated with a different data property of data stored in the cache segment; configure software executing on the processor to direct cache accesses to one of the cache segments based on a corresponding data property of the cache accesses by the software; and process, by the processor, a data access operation from the software executing on the processor, based on an identifier of a cache segment in one of an effective address provided by the software or a page table entry corresponding to the effective address provided by the software, wherein the identifier comprises a cache segmentation enablement bit that indicates cache segmenting is used with a page frame corresponding to the page table entry and one or more cache segment selection bits that each indicate a cache segment to be used for caching the cache lines from the page frame corresponding to the page table entry. ### Claim 12 (depends on 11) The computer program product of claim 11, wherein the identifier of the cache segment is in the page table entry in a hardware page table. ### Claim 13 (depends on 12) The computer program product of claim 12, wherein the one or more cache segment selection bits identify a specific cache segment in which data, corresponding to a page frame of a page corresponding to the page table entry, is stored. ### Claim 14 (depends on 11) The computer program product of claim 11, wherein the identifier of the cache segment is a cache segment selection bit of the one or more cache section selection bits in the effective address. ### Claim 15 (depends on 14) The computer program product of claim 14, wherein segmenting the cache comprises mapping a first range of effective addresses to a first cache segment and associating a first cache segment selection bit setting in effective addresses with the first cache segment, and mapping a second range of effective addresses to a second cache segment and associating a second cache segment selection bit setting in effective address with the second cache segment. ### Claim 16 (depends on 11) The computer program product of claim 11, wherein the software executing on the processor controls, via operating system calls, mapping of data utilized by the software to a particular cache segment or set of cache segments at a page level via a page table entry cache segment enable/disable bit and at least one page table entry cache segment selection bit in the page table entry in a hardware page table. ### Claim 17 (depends on 11) The computer program product of claim 11, wherein data property of the data comprises a data longevity property that specifies whether corresponding data is to be placed in a long term data cache segment or a short term data cache segment of the cache, and wherein the identifier of a cache segment identifies one of the long term data cache segment or the short term data cache segment of the cache. ### Claim 18 (depends on 11) The computer program product of claim 11, wherein an operating system executing in the data processing system restricts a relatively low priority process of the software executing on the processor to a particular cache segment or set of cache segments by setting cache segment enable/disable bits and cache segment selection bits in page table entries of all page frames used by the relatively low priority process to point to a same cache segment. ### Claim 19 (depends on 11) The computer program product of claim 11, wherein a virtual machine monitor (VMM) executing in the data processing system restricts a logical partition (LPAR) or virtual machine executing in the data processing system to a particular cache segment or set of cache segments, by setting cache segment enable/disable bits and cache segment selection bits in page table entries of all page frames used by the LPAR or virtual machine to point to a same cache segment. ### Claim 20 An apparatus comprising: a processor; and a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to: segment a cache memory of a cache subsystem of the apparatus, such that the cache memory comprises a plurality of cache segments, wherein each cache segment in the plurality of cache segments is associated with a different data property of data stored in the cache segment; configure software executing on the processor to direct cache accesses to one of the cache segments based on a corresponding data property of the cache accesses by the software; and process, by the processor, a data access operation from the software executing on the processor, based on an identifier of a cache segment in one of an effective address provided by the software or a page table entry corresponding to the effective address provided by the software, wherein the identifier comprises a cache segmentation enablement bit that indicates cache segmenting is used with a page frame corresponding to the page table entry and one or more cache segment selection bits that each indicate a cache segment to be used for caching the cache lines from the page frame corresponding to the page table entry.