# US 10,372,612 B2 · Apparatuses and methods for compute enabled cache

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- Number: US 10,372,612 B2
- Document ID: US10372612B2
- Status: Granted
- Kind: B2
- Application number: 16/126,169
- Filed: 2018-09-10
- Published: 2019-01-17
- Granted: 2019-08-06
- Earliest claimed: 2015-05-28
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Richard C. Murphy
- Web page: https://patentgrep.com/patent/US10372612B2

## CPC

- G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/084: with a shared cache
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G06F 2212/1012: Design facilitation
- G06F 2212/1044: Space efficiency improvement
- G06F 2212/283: Plural cache memories
- G06F 2212/6032: Way prediction in set-associative cache
- G11C 11/4094: Bit-line management or control circuits
- G11C 19/00: Digital stores in which the information is moved stepwise, e.g. shift registers
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.

## Claims

### Claim 1

An apparatus, comprising:
a memory configured to store cache data and having:
a memory array;
a sensing circuitry comprising a plurality of sense amplifiers and a plurality of compute components to perform logical operations; and
a controller coupled to the memory array, the controller configured to:
create a block select as metadata to a cache line to control alignment of cache blocks within the memory array; and
create a subrow select as metadata to the cache line to control placement of the cache line on a particular row in the memory array to align the cache line to one or more of the plurality of sense amplifiers.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the memory is a last layer cache (LLC) memory.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the plurality of sense amplifiers are configured to access and to operate on cached data in the LLC memory without moving the cached data to a higher level in the memory.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein:
the block select enables an offset to the cache line; and
the subrow select enables multiple sets to a set associative cache.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the block select provides an offset to a page in a dynamic random access memory (DRAM) page.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the controller is configured to:
change the block select and the subrow select;
relocate the cached data transparently to a host processor; and
wherein the block select and the subrow select are not part of an address space of the host processor.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the memory controller is configured to store a copy of the block select and the subrow select internal to the host processor.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the memory controller is configured to:
use the block select to control alignment of cached data in the memory array in the memory; and
use the subrow select to control resource allocation in the memory array.

### Claim 9

An apparatus, comprising:
a memory device comprising:
an array of memory cells;
sensing circuitry coupled to the array; and
a controller coupled to the array and sensing circuitry and configured to:
receive a cache line having block select and subrow select metadata; and
operate on the block select and subrow select metadata to:
control alignment of cache blocks in the array; and
allow the cache line to be placed on a particular row of the array to align the cache line to the sensing circuitry.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the apparatus further includes a cache controller to:
create the block select metadata and insert to the cache line; and
create the subrow select metadata and insert to the cache line.

### Claim 11 (depends on 9)

The apparatus of claim 9, wherein the block select metadata and the row select metadata are stored internal to the memory device and are transparent to an address space of a processing resource of the host.

### Claim 12 (depends on 9)

The apparatus of claim 9, wherein each cache line is handled as multiple vectors of different bit length values.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein each of the different bit length values of the multiple vectors is further subdivided into multiple elements.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the controller is configured to use the subrow select metadata to select a subarray to place an element of the multiple elements of a vector.

### Claim 15 (depends on 9)

The apparatus of claim 9, wherein the controller is configured to:
store the cache block in the array; and
retrieve a cache line to perform logical operations with the plurality of compute components and the plurality of sense amplifiers.

### Claim 16

A method for operating a cache memory, comprising:
creating a block select as metadata to a cache line to control alignment of cache blocks in a memory array of the cache memory comprising sensing circuitry including a plurality of sense amplifiers and a plurality of compute components to perform logical operations; and
creating a subrow select as metadata to the cache line to control placement of at least a portion of the cache line on multiple rows in the memory array.

### Claim 17 (depends on 16)

The method of claim 16, wherein the method comprises:
receiving the block select and the subrow select to a memory controller in a processing in memory (PIM) device, the memory array is a dynamic random access memory (DRAM) array, wherein the PIM device comprises:
the sensing circuitry coupled to the memory array, the sensing circuitry including the plurality of sense amplifiers and the plurality of compute components configured to implement logical operations;
storing the cache block in the memory array; and
retrieving at least a portion of the cache line to perform logical operations with the plurality of compute components and the plurality of sense amplifiers.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
using the block select to choose which part of a row in the memory array having a first bit width to access as a chunk having a second bit width as part of an array access request;
using the block select and the subrow select in a repeated manner to allow a cache line to be split and placed differently in a bank of the memory array.

### Claim 19 (depends on 18)

The method of claim 18, wherein the memory array is in a processing in memory (PIM) based device and further comprising:
placing a plurality of different cache blocks in a plurality of different banks in a dynamic random access memory (DRAM) to allow multiple mapped single cache lines.

### Claim 20 (depends on 19)

The method of claim 19, further comprising managing a first bit length cache line on a second bit length interface such that multiple second bit length chunks can each have a different alignment.