# US 10,372,611 B2 · Deferred response to a prefetch request > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,611 B2 - Document ID: US10372611B2 - Status: Granted - Kind: B2 - Application number: 16/174,368 - Filed: 2018-10-30 - Published: 2019-03-07 - Granted: 2019-08-06 - Earliest claimed: 2015-11-10 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Michael Karl Gschwind; Valentina Salapura; Chung-Lung K. Shum - Web page: https://patentgrep.com/patent/US10372611B2 ## CPC - G06F 12/0862: with prefetch - G06F 3/061: {Improving I/O performance} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0683: {Plurality of storage devices} - G06F 9/30: Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) - G06F 9/467: {Transactional memory (G06F9/528 takes precedence)} - G06F 12/0811: with multilevel cache hierarchies - G06F 12/0815: Cache consistency protocols - G06F 12/084: with a shared cache - G06F 12/0842: for multiprocessing or multitasking - G06F 12/0844: Multiple simultaneous or quasi-simultaneous cache accessing - G06F 12/0875: with dedicated cache, e.g. instruction or stack - G06F 15/76: Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) - G06F 2212/1008: Correctness of operation, e.g. memory ordering - G06F 2212/1016: Performance improvement - G06F 2212/1024: Latency reduction - G06F 2212/452: Instruction code - G06F 2212/507: using speculative control - G06F 2212/602: Details relating to cache prefetching - G06F 2212/6028: Prefetching based on hints or prefetch instructions - G06F 2212/62: Details of cache specific to multiprocessor cache arrangements - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Modifying prefetch request processing. A prefetch request is received by a local computer from a remote computer. The local computer responds to a determination that execution of the prefetch request is predicted to cause an address conflict during an execution of a transaction of the local processor by comparing a priority of the prefetch request with a priority of the transaction. Based on a result of the comparison, the local computer modifies program instructions that govern execution of the program instructions included in the prefetch request to include program instruction to perform one or both of: (i) a quiesce of the prefetch request prior to execution of the prefetch request, and (ii) a delay in execution of the prefetch request for a predetermined delay period. ## Claims ### Claim 1 A method to modify prefetch request processing, the method comprising: receiving, by a local processor of a group of one or more processors of a local computer, a prefetch request from a remote processor of a remote computer that is in communication with the local computer; prior to execution of program instructions included in the prefetch request, determining, by the group of one or more processors, whether execution of the prefetch request is predicted to cause an address conflict by accessing a memory address that is accessed during an execution of a transaction of the local processor; responsive to a determination that execution of the prefetch request is predicted to cause a conflict during the execution of the transaction, comparing, by the group of one or more processors, a priority of the prefetch request with a priority of the transaction; and based, at least in part, on a result of the comparison, modifying, by the group of one or more processors, one or more program instructions that govern execution of the program instructions included in the prefetch request to include program instruction to perform one or both of: (i) a quiesce of the prefetch request prior to execution of the prefetch request, (ii) a delay in execution of the prefetch request for a predetermined delay period. ### Claim 2 (depends on 1) The method of claim 1, further comprising: responsive to at least one of (i) a determination that the local processor has no transaction, and (ii) a determination that an execution of the prefetch request is not predicted to cause the conflict during the execution of the transaction of the local processor, executing, by the group of one or more processors, the prefetch request, wherein the prefetch request is one of a read prefetch instruction or a write prefetch instruction. ### Claim 3 (depends on 1) The method of claim 1, wherein quiescing the prefetch request comprises: monitoring, by the group of one or more processors, one or more conditions in the local processor and executing the prefetch request when the one or more conditions meet a criterion. ### Claim 4 (depends on 1) The method of claim 1, further comprising: responsive to the determination that execution of the prefetch request is predicted to cause the conflict during the execution of the transaction, delaying, by the group of one or more processors, execution of the prefetch request for the delay period, wherein the delay period is based on a prefetch time horizon that is associated with a prefetch operation that is divided into time steps with each time step specified in a preset number of cycles that a receiver of the prefetch request uses to manage the prefetch request; and performing, by the group of one or more processors, an action at an end of the delay period that is based on one or more conditions in the local processor, wherein the action includes one or more of (i) aborting the prefetch request, (ii) further delaying execution of the prefetch request, (iii) quiescing the prefetch request, and (iv) executing the prefetch request. ### Claim 5 (depends on 4) The method of claim 4, further comprising: notifying, by the group of one or more processors, the remote processor of the action taken at the end of the delay period. ### Claim 6 (depends on 4) The method of claim 4, wherein delaying the prefetch request comprises: queuing, by the group of one or more processors, the prefetch request in a queue of a group of one or more queues. ### Claim 7 (depends on 6) The method of claim 6, further comprising: notifying, by the group of one or more processors, the remote processor that the prefetch request was queued. ### Claim 8 (depends on 5) The method of claim 5, wherein each queue in the one or more queues holds all prefetch requests from a same remote processor and only prefetch requests from the same remote processor. ### Claim 9 (depends on 5) The method of claim 5, wherein the group of one or more queues includes one or both of: (i) at least one queue, of the one or more queues, that holds all prefetch requests for exclusive ownership and only prefetch requests for exclusive ownership, and (ii) at least one queue, of the one or more queues, that holds all prefetch requests for shared ownership and only prefetch requests for shared ownership. ### Claim 10 A computer program product to modify prefetch request processing, the program instructions comprising: one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising: program instructions to receiving, by a local processor of a group of one or more processors of a local computer, a prefetch request from a remote processor of a remote computer that is in communication with the local computer; program instructions to, prior to execution of program instructions included in the prefetch request, determine whether execution of the prefetch request is predicted to cause an address conflict by accessing a memory address that is accessed during an execution of a transaction of the local processor; program instructions to respond to a determination that execution of the prefetch request is predicted to cause a conflict during the execution of the transaction, comparing a priority of the prefetch request with a priority of the transaction; and program instructions to, based, at least in part, on a result of the comparison, modify one or more program instructions that govern execution of the program instructions included in the prefetch request to include program instruction to perform one or both of: (i) a quiesce of the prefetch request prior to execution of the prefetch request, and (ii) a delay in execution of the prefetch request for a predetermined delay period. ### Claim 11 (depends on 10) The computer program product of claim 10, further comprising: program instructions to respond to at least one of (i) a determination that the local processor has no transaction, and (ii) a determination that an execution of the prefetch request is not predicted to cause the conflict during the execution of the transaction of the local processor, by executing the prefetch request, wherein the prefetch request is one of a read prefetch instruction or a write prefetch instruction. ### Claim 12 (depends on 10) The computer program product of claim 10, wherein quiescing the prefetch request includes monitoring one or more conditions in the local processor and executing the prefetch request when the one or more conditions meet a criterion. ### Claim 13 (depends on 10) The computer program product of claim 10, further comprising: program instructions to respond to the determination that execution of the prefetch request is predicted to cause the conflict during the execution of the transaction by delaying execution of the prefetch request for the delay period, wherein the delay period is based on a prefetch time horizon that is associated with a prefetch operation that is divided into time steps with each time step specified in a preset number of cycles that a receiver of the prefetch request uses to manage the prefetch request; and program instructions to perform an action at an end of the delay period that is based on one or more conditions in the local processor, wherein the action includes one or more of (i) aborting the prefetch request, (ii) further delaying execution of the prefetch request, (iii) quiescing the prefetch request, and (iv) executing the prefetch request. ### Claim 14 (depends on 13) The computer program product of claim 13, further comprising: program instructions to notify the remote processor of the action taken at the end of the delay period. ### Claim 15 (depends on 13) The computer program product of claim 13, wherein delaying the prefetch request comprises queuing the prefetch request in a queue in a group of one or more queues. ### Claim 16 (depends on 15) The computer program product of claim 15, further comprising: program instructions to notify the remote processor that the prefetch request was queued. ### Claim 17 (depends on 14) The computer program product of claim 14, wherein the group of one or more queues includes one or both of: (i) at least one queue, of the one or more queues, that holds all prefetch requests for exclusive ownership and only prefetch requests for exclusive ownership, and (ii) at least one queue, of the one or more queues, that holds all prefetch requests for shared ownership and only prefetch requests for shared ownership. ### Claim 18 (depends on 10) The computer program product of claim 10, wherein quiescing the prefetch request includes monitoring one or more conditions in the local processor and executing the prefetch request when the one or more conditions meet a criterion. ### Claim 19 A computer system to modify prefetch request processing, the computer system comprising: one or more computer processors; one or more computer readable storage medium; program instructions stored on the computer readable storage medium for execution by at least one of the one or more processors, the program instructions comprising: program instructions to receiving, by a local processor of a group of one or more processors of a local computer, a prefetch request from a remote processor of a remote computer that is in communication with the local computer; program instructions to, prior to execution of program instructions included in the prefetch request, determine whether execution of the prefetch request is predicted to cause an address conflict by accessing a memory address that is accessed during an execution of a transaction of the local processor; program instructions to respond to a determination that execution of the prefetch request is predicted to cause a conflict during the execution of the transaction, comparing a priority of the prefetch request with a priority of the transaction; and program instructions to, based, at least in part, on a result of the comparison, modify one or more program instructions that govern execution of the program instructions included in the prefetch request to include program instruction to perform one or both of: (i) a quiesce of the prefetch request prior to execution of the prefetch request, and (ii) a delay in execution of the prefetch request for a predetermined delay period. ### Claim 20 (depends on 19) The computer system of claim 19, further comprising: program instructions to respond to at least one of (i) a determination that the local processor has no transaction, and (ii) a determination that an execution of the prefetch request is not predicted to cause the conflict during the execution of the transaction of the local processor, by executing the prefetch request, wherein the prefetch request is one of a read prefetch instruction or a write prefetch instruction.