# US 10,372,609 B2 · Fast cache warm-up > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,609 B2 - Document ID: US10372609B2 - Status: Granted - Kind: B2 - Application number: 15/704,130 - Filed: 2017-09-14 - Published: 2019-03-14 - Granted: 2019-08-06 - Earliest claimed: 2017-09-14 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Sagi Weiss - Web page: https://patentgrep.com/patent/US10372609B2 ## CPC - G06F 12/0811: with multilevel cache hierarchies - G06F 12/082: {Associative directories (G06F12/0822 takes precedence)} - G06F 12/0877: Cache access modes - G06F 12/0879: Burst mode - G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) - G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing - G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems - G06F 2212/1024: Latency reduction - G06F 2212/1028: Power efficiency - G06F 2212/6012: of operating mode, e.g. cache mode or local memory mode - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract An embodiment of a semiconductor package apparatus may include technology to determine if a memory request for a second level memory results in a miss with respect to a first level memory, determine if a range of the second level memory corresponding to the memory request is unwritten, if the memory request results in the miss with respect to the first level memory, and blank a corresponding range of the first level memory if the range of the second level memory corresponding to the memory request is determined to be unwritten. Other embodiments are disclosed and claimed. ## Claims ### Claim 1 An electronic processing system, comprising: a processor; a multi-level memory communicatively coupled to the processor, the multi-level memory including a first level memory and a second level memory; and logic communicatively coupled to the processor and the multi-level memory to: determine if a memory request for the second level memory results in a miss with respect to the first level memory, determine if a range of the second level memory corresponding to the memory request is unwritten when it is determined that the memory request results in the miss with respect to the first level memory, and blank a range of the first level memory corresponding to the range of the second level memory based on a determination that the second level memory is unwritten. ### Claim 2 (depends on 1) The system of claim 1, wherein the logic is further to: set an indicator flag to indicate whether any range of the second level memory is unwritten. ### Claim 3 (depends on 2) The system of claim 2, wherein the logic is further to: determine if the range of the second level memory corresponding to the memory request is unwritten based on the indicator flag. ### Claim 4 (depends on 2) The system of claim 2, wherein the logic is further to: zero the corresponding range of the first level memory if the indicator flag indicates that the range of the second level memory corresponding to the memory request is unwritten. ### Claim 5 (depends on 1) The system of claim 1, wherein the logic is further to: determine if the range of the second level memory corresponding to the memory request is unwritten based on an indicator bit in a tag array. ### Claim 6 (depends on 1) The system of claim 1, wherein a size of the range of the second level memory corresponds to one of a size of the entire second level memory, a size of a pre-determined address range, a size of a super line, a size of a set of ways, and a size of a subset of ways. ### Claim 7 A semiconductor package apparatus, comprising: a substrate; and logic coupled to the substrate, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the substrate to: determine if a memory request for a second level memory results in a miss with respect to a first level memory, determine if a range of the second level memory corresponding to the memory request is unwritten when it is determined that the memory request results in the miss with respect to the first level memory, and blank a range of the first level memory corresponding to the range of the second level memory based on a determination that the second level memory is unwritten. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the logic is further to: set an indicator flag to indicate whether any range of the second level memory is unwritten. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the logic is further to: determine if the range of the second level memory corresponding to the memory request is unwritten based on the indicator flag. ### Claim 10 (depends on 8) The apparatus of claim 8, wherein the logic is further to: zero the corresponding range of the first level memory if the indicator flag indicates that the range of the second level memory corresponding to the memory request is unwritten. ### Claim 11 (depends on 7) The apparatus of claim 7, wherein the logic is further to: determine if the range of the second level memory corresponding to the memory request is unwritten based on an indicator bit in a tag array. ### Claim 12 (depends on 7) The apparatus of claim 7, wherein a size of the range of the second level memory corresponds to one of a size of the entire second level memory, a size of a pre-determined address range, a size of a super line, a size of a set of ways, and a size of a subset of ways. ### Claim 13 A method of controlling a memory, comprising: determining if a memory request for a second level memory results in a miss with respect to a first level memory; determining if a range of the second level memory corresponding to the memory request is unwritten when it is determined that the memory request results in the miss with respect to the first level memory; and blanking a range of the first level memory corresponding to the range of the second level memory based on a determination that the second level memory is unwritten. ### Claim 14 (depends on 13) The method of claim 13, further comprising: setting an indicator flag to indicate whether any range of the second level memory is unwritten. ### Claim 15 (depends on 14) The method of claim 14, further comprising: determining if the range of the second level memory corresponding to the memory request is unwritten based on the indicator flag. ### Claim 16 (depends on 14) The method of claim 14, further comprising: zeroing the corresponding range of the first level memory if the indicator flag indicates that the range of the second level memory corresponding to the memory request is unwritten. ### Claim 17 (depends on 13) The method of claim 13, further comprising: determining if the range of the second level memory corresponding to the memory request is unwritten based on an indicator bit in a tag array. ### Claim 18 (depends on 13) The method of claim 13, wherein a size of the range of the second level memory corresponds to one of a size of the entire second level memory, a size of a pre-determined address range, a size of a super line, a size of a set of ways, and a size of a subset of ways. ### Claim 19 A method of controlling a memory, comprising: determining if a memory request for a second level memory results in a miss with respect to a first level memory; determining if a range of the second level memory corresponding to the memory request is unwritten when it is determined that the memory request results in the miss with respect to the first level memory; and blanking a range of the first level memory corresponding to the range of the second level memory based on a determination that the second level memory is unwritten. ### Claim 20 (depends on 19) The at least one computer readable medium of claim 19, comprising a further set of instructions, which when executed by the computing device, cause the computing device to: set an indicator flag to indicate whether any range of the second level memory is unwritten. ### Claim 21 (depends on 20) The at least one computer readable medium of claim 20, comprising a further set of instructions, which when executed by the computing device, cause the computing device to: determine if the range of the second level memory corresponding to the memory request is unwritten based on the indicator flag. ### Claim 22 (depends on 20) The at least one computer readable medium of claim 20, comprising a further set of instructions, which when executed by the computing device, cause the computing device to: zero the corresponding range of the first level memory if the indicator flag indicates that the range of the second level memory corresponding to the memory request is unwritten. ### Claim 23 (depends on 19) The at least one computer readable medium of claim 19, comprising a further set of instructions, which when executed by the computing device, cause the computing device to: determine if the range of the second level memory corresponding to the memory request is unwritten based on an indicator bit in a tag array. ### Claim 24 (depends on 19) The at least one computer readable medium of claim 19, wherein a size of the range of the second level memory corresponds to one of a size of the entire second level memory, a size of a pre-determined address range, a size of a super line, a size of a set of ways, and a size of a subset of ways.