# US 10,372,608 B2 · Split head invalidation for consumer batching in pointer rings

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- Number: US 10,372,608 B2
- Document ID: US10372608B2
- Status: Granted
- Kind: B2
- Application number: 15/691,100
- Filed: 2017-08-30
- Published: 2019-02-28
- Granted: 2019-08-06
- Earliest claimed: 2017-08-30
- Assignees: Red Hat, Inc.
- Applicants: Red Hat, Inc.
- Inventors: Michael Tsirkin
- Web page: https://patentgrep.com/patent/US10372608B2

## CPC

- G06F 12/0808: with cache invalidating means (G06F12/0815 takes precedence)
- G06F 9/45558: {Hypervisor-specific management and integration aspects}
- G06F 9/544: {Buffers; Shared memory; Pipes}
- G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 2009/45583: {Memory management, e.g. access or allocation}
- G06F 2009/45595: {Network integration; Enabling network access in virtual machine instances}
- G06F 2212/224: Disk storage
- G06F 2212/621: Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A split head invalidation system includes a first memory including a ring buffer, a second memory, and a processor in communication with the first memory. The processor includes a consumer processor and a producer processor. The consumer processor is configured to maintain a head and tail pointer, detect a request to copy a memory entry from the ring buffer, and consume the memory entry. Consuming the memory entry includes iteratively testing a value associated with the memory entry in a slot indicated by the head pointer, retrieving the respective memory entry from the slot, and advancing the head pointer to the next slot until reaching a threshold quantity of slots. Additionally, the consumer processor is configured to invalidate each slot from the head pointer to the tail pointer after reaching the threshold quantity.

## Claims

### Claim 1

A system comprising:
a first memory including a ring buffer having a plurality of slots;
a second memory; and
at least one processor in communication with the first memory, wherein the at least one processor includes a consumer processor and a producer processor, and the consumer processor is configured to:
maintain a head pointer and a tail pointer,
detect a request to copy at least one memory entry from the ring buffer to the second memory,
consume the at least one memory entry from the ring buffer, including:
(i) test a respective value associated with a respective memory entry in a first slot of the plurality of slots, wherein the first slot is indicated by the head pointer,
(ii) responsive to receiving a valid value from the test, retrieve the respective memory entry from the first slot,
(iii) advance the head pointer to a second slot while the location of the tail pointer remains unchanged, and
(iv) iterating (i), (ii), and (iii) for each successive slot that the head pointer advances to until reaching a threshold quantity of slots, and
responsive to a quantity of slots reaching the threshold quantity of slots, invalidate each slot between the head pointer and the tail pointer.

### Claim 2 (depends on 1)

The system of claim 1, wherein the consumer processor is configured to advance the tail pointer to the location of the head pointer after invalidating each slot between the head pointer and the tail pointer.

### Claim 3 (depends on 1)

The system of claim 1, wherein the head pointer and the tail pointer are maintained in the same cache line.

### Claim 4 (depends on 1)

The system of claim 1, wherein the head pointer and the tail pointer are indices.

### Claim 5 (depends on 1)

The system of claim 1, wherein the threshold quantity of slots occupy an integer number of cache lines.

### Claim 6 (depends on 1)

The system of claim 1, wherein the head pointer and the tail pointer start at the same slot.

### Claim 7 (depends on 1)

The system of claim 1, further comprising a counter, wherein the consumer processor is configured to track the quantity of slots with the counter.

### Claim 8 (depends on 1)

The system of claim 1, wherein the consumer processor compares the location of the head pointer and the tail pointer to track the quantity of slots that the head pointer advances.

### Claim 9 (depends on 1)

The system of claim 1, wherein the consumer processor and the producer processor are on different cores of the same physical processor.

### Claim 10 (depends on 1)

The system of claim 1, wherein the consumer processor and the producer processor are different physical processors.

### Claim 11 (depends on 1)

The system of claim 1, wherein the at least one memory entry is at least one packet address and the second memory is a virtual machine memory.

### Claim 12

A method comprising:
maintaining, by a consumer processor, a head pointer and a tail pointer;
detecting, by a consumer processor, a request to copy at least one memory entry from a ring buffer having a plurality of slots;
consuming, by the consumer processor, the at least one memory entry from the ring buffer, including:
(i) testing, by the consumer processor, a first value associated with a respective memory entry in a first slot of the plurality of slots, wherein the first slot is indicated by the head pointer,
(ii) responsive to receiving a valid value from the test, retrieve, by the consumer processor, the respective memory entry from the first slot,
(iii) advancing, by the consumer processor, the head pointer to a second slot while the location of the tail pointer remains unchanged, and
(iv) iterating, by the consumer processor, (i), (ii), and (iii) for each successive slot that the head pointer advances to until reaching a threshold quantity of slots; and
responsive to a quantity of slots reaching the threshold quantity of slots, invalidating, by the consumer processor, each slot between the head pointer and the tail pointer.

### Claim 13 (depends on 12)

The method of claim 12, further comprising tracking, by the consumer processor, the quantity of slots the head pointer advances to, wherein tracking the quantity of slots used includes comparing the head pointer and the tail pointer.

### Claim 14 (depends on 12)

The method of claim 12, further comprising copying, by the consumer processor, the respective memory entries to a second memory.

### Claim 15 (depends on 12)

The method of claim 12, further comprising advancing, by the consumer processor, the tail pointer to the location of the head pointer.

### Claim 16 (depends on 12)

The method of claim 12, wherein the head pointer and the tail pointer are maintained in the same cache line in the memory.

### Claim 17 (depends on 12)

The method of claim 12, wherein the consumer processor detects a request from one of the virtual machine and the producer processor.

### Claim 18 (depends on 12)

The method of claim 12, wherein invalidating each slot between the head pointer and the tail pointer includes invalidating each slot behind a third slot indicated by the head pointer to the first slot indicated by the tail pointer, which includes invalidating the first slot indicated by the tail pointer.

### Claim 19 (depends on 12)

The method of claim 12, wherein the consumer processor advances the head pointer to a third slot and the consumer processor invalidates the second slot and the first slot, wherein the first slot, the second slot, and the third slot are successive slots in the ring buffer.

### Claim 20

A non-transitory machine-readable medium storing code, which when executed by a consumer processor, is configured to:
maintain a head pointer and a tail pointer;
detect a request to copy a at least one memory entry from a ring buffer having a plurality of slots;
consume the at least one memory entry from the ring buffer, including:
(i) test a first value associated with a respective memory entry in a first slot of the plurality of slots, wherein the first slot is indicated by the head pointer,
(ii) responsive to receiving a valid value from the test, retrieve the respective memory entry from the first slot,
(iii) advance the head pointer to a second slot while the location of the tail pointer remains unchanged, and
(iv) iterate (i), (ii), and (iii) for each successive slot that the head pointer advances to until reaching a threshold quantity of slots; and
responsive to the quantity of slots reaching the threshold quantity of slots, invalidate each slot between the head pointer and the tail pointer.
