# US 10,372,603 B2 · Handling of unaligned writes

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- Number: US 10,372,603 B2
- Document ID: US10372603B2
- Status: Granted
- Kind: B2
- Application number: 15/822,881
- Filed: 2017-11-27
- Published: 2019-05-30
- Granted: 2019-08-06
- Earliest claimed: 2017-11-27
- Assignees: Western Digital Technologies, Inc.
- Applicants: Western Digital Technologies, Inc.
- Inventors: Ramanathan Muthiah; Ramkumar Ramamurthy; Balaji Thraksha Venkataramanan
- Web page: https://patentgrep.com/patent/US10372603B2

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 3/061: {Improving I/O performance}
- G06F 3/064: {Management of blocks}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 9/3013: {according to data content, e.g. floating-point registers, address registers}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/10: Programming or data input circuits
- G06F 2212/1024: Latency reduction
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 2211/5622: Concurrent multilevel programming of more than one cell
- G11C 2211/5641: Multilevel memory having cells with different number of storage levels
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

One or more control circuits of a storage system are configured to consolidate the sensing of pre-pad and/or post-pad data for one unaligned write command with the transferring of previously sensed pre-pad and/or post-pad data for another unaligned write command. By consolidating the sensing and transferring, considerable time is saved when programming data for a set of two or more unaligned write commands. Also, in one aspect, a single programming operation is performed for multiple unaligned write commands. Some conventional solutions may need to perform a programming operation for each unaligned write command. Hence, considerable programming time is saved by the storage system. Moreover, write amplification may be reduced by the storage system.

## Claims

### Claim 1

An apparatus comprising:
a memory die having memory cells;
a data buffer; and
one or more control circuits configured to:
receive unaligned data into the data buffer, the unaligned data for a plurality of unaligned write commands;
concurrently sense pad data from memory cells on the memory die for one of the unaligned write commands and transfer pad data previously sensed from memory cells on the memory die to the data buffer for another of the unaligned write commands;
transfer aligned data for each of the unaligned write commands from the data buffer to the memory die; and
program the aligned data into a group of memory cells on the memory die.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the one or more control circuits are further configured to:
concurrently program all of the aligned data into the group of memory cells on the memory die.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the one or more control circuits are further configured to:
concurrently sense pad data from memory cells on the memory die for one of the unaligned write commands and transfer pad data previously sensed from memory cells on the memory die to the data buffer for another of the unaligned write commands for “n−1” pairs of “n” unaligned write commands.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the memory die comprises a first set of data registers and a second set of data registers, wherein to concurrently sense pad data from memory cells on the memory die for one of the unaligned write commands and transfer pad data previously sensed from memory cells on the memory die to the data buffer for another of the unaligned write commands the one or more control circuits are further configured to:
sense a first set of memory cells on the memory die in order to store pad data for a first of the unaligned write commands into the first set of data registers;
transfer the pad data for the first unaligned write command from the first set of data registers to the second set of data registers; and
concurrently sense a second set of memory cells on the memory die in order to store pad data for a second of the unaligned write commands into the first set of data registers and transfer the pad data for the first unaligned write command from the second set of data registers to the data buffer.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the one or more control circuits are further configured to:
concurrently program all of the aligned data for each of the unaligned write commands from the first set of data registers into the group of memory cells.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the one or more control circuits are further configured to:
program all of the aligned data for the plurality of unaligned write commands into the group of memory cells on the memory die in a single programming operation per plane.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the one or more control circuits are further configured to:
identify a sufficient number of unaligned write commands in a command queue such that the aligned data is one maximum unit of programming.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the group of memory cells reside on a plurality of planes in the memory die.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the one or more control circuits are further configured to:
select a sufficient number of unaligned write commands for a single level cell (SLC) to multi-level cell (MLC) fold operation;
divide the unaligned write commands into a set for each of a plurality of SLC groups of memory cells;
for each of the set of unaligned write commands: i) receive the unaligned data to the data buffer, ii) concurrently sense the pad data from memory cells on the memory die for one of the unaligned write commands in the set and transfer pad data previously sensed from memory cells on the memory die to the data buffer for another of the unaligned write commands in the set; iii) transfer aligned data for each of the unaligned write commands in the set from the data buffer to the memory die; and iv) program the aligned data for the set into a group of SLC memory cells on the memory die; and
transfer the data from the plurality of SLC groups of memory cells into an MLC group of memory cells on the memory die.

### Claim 10

A method of operating a memory system, the method comprising:
identifying a plurality of unaligned write commands in a command queue of a memory controller;
transferring unaligned data for the plurality of unaligned write commands to a data buffer of the memory controller;
consolidating sensing of pad data from memory cells on a memory die for one of the unaligned write commands with transferring pad data previously sensed from memory cells on the memory die to the data buffer for another of the unaligned write commands, wherein transferring the unaligned data and transferring the pad data previously sensed forms a complete fragment in the data buffer for each unaligned write command;
transferring a complete fragment of data for each of the unaligned write commands from the data buffer to the memory die; and
programming the complete fragments of data that were transferred to the memory die into a group of memory cells on the memory die.

### Claim 11 (depends on 10)

The method of claim 10, wherein programming the complete fragments of data that were transferred to the memory die into a group of memory cells on the memory die comprises:
concurrently programming all of the complete fragments of data that were transferred to the memory die into the group of memory cells on the memory die.

### Claim 12 (depends on 10)

The method of claim 10, wherein consolidating the sensing of pad data from memory cells on the memory die for one of the unaligned write commands with the transferring previously sensed pad data from the memory die to the data buffer for another of the unaligned write commands is performed for “n−1” pairs of “n” unaligned write commands.

### Claim 13 (depends on 10)

The method of claim 10, wherein consolidating the sensing of pad data from memory cells on the memory die for one of the unaligned write commands with the transferring previously sensed pad data from the memory die to the data buffer for another of the unaligned write commands comprises:
sensing a first set of memory cells on the memory die in order to store pad data for a first of the unaligned write commands into a first set of data latches;
transferring the pad data for the first unaligned write command from the first set of data latches to a second set of data latches; and
sensing a second set of memory cells on the memory die in order to store pad data for a second of the unaligned write commands into the first set of data latches while transferring the pad data for the first unaligned write command from the second set of data latches to the data buffer.

### Claim 14 (depends on 13)

The method of claim 13, wherein programming the complete fragment of data that was transferred to the memory die into a group of memory cells on the memory die comprises:
concurrently programming each of the complete fragments of data for each of the unaligned write commands from the first set of data latches into the group of memory cells.

### Claim 15 (depends on 10)

The method of claim 10, wherein programming each of the complete fragments of data that were transferred to the memory die into a group of memory cells on the memory die comprises:
programming one maximum unit of programming in the memory die.

### Claim 16 (depends on 10)

The method of claim 10, wherein identifying the plurality of unaligned write commands comprises identifying random write commands.

### Claim 17

A non-volatile memory system comprising:
a memory die having memory cells;
a data buffer;
unaligned write command identification means for identifying a plurality of unaligned write commands in a command queue of a memory controller;
first data transfer means for transferring unaligned data for the plurality of unaligned write commands to a data buffer of the memory controller;
consolidating means for consolidating sensing of pad data from memory cells on a memory die for one of the unaligned write commands with transferring pad data previously sensed from memory cells on the memory die to the data buffer for another of the unaligned write commands;
second data means for transferring a complete fragment of data for each of the unaligned write commands from the data buffer to the memory die; and
programming means for programming the complete fragment of data that was transferred to the memory die into a group of memory cells on the memory die.

### Claim 18 (depends on 17)

The non-volatile memory system of claim 17, wherein the programming means is further for concurrently programming the complete fragment of data that was transferred to the memory die into the group of memory cells on the memory die.

### Claim 19 (depends on 17)

The non-volatile memory system of claim 17, wherein the consolidating means is further for consolidating the sensing of pad data from memory cells on the memory die for one of the unaligned write commands with the transferring previously sensed pad data from the memory die to the data buffer for another of the unaligned write commands is performed for “n−1” pairs of “n” unaligned write commands.

### Claim 20 (depends on 17)

The non-volatile memory system of claim 17, wherein:
the unaligned write command identification means is further for identifying a sufficient number of unaligned write commands in the command queue such that the complete fragments of data are one maximum unit of programming; and
the programming means is further for programming all of the complete fragments in order to program the maximum unit of programming.