# US 10,372,534 B2 · Method of operating memory device using a compressed party difference, memory device using the same and memory system including the device

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- Number: US 10,372,534 B2
- Document ID: US10372534B2
- Status: Granted
- Kind: B2
- Application number: 15/270,292
- Filed: 2016-09-20
- Published: 2018-03-22
- Granted: 2019-08-06
- Earliest claimed: 2016-09-20
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Amit Berman; Uri Beitler; Jun Jin Kong
- Web page: https://patentgrep.com/patent/US10372534B2

## CPC

- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- G06F 11/108: {Parity data distribution in semiconductor storages, e.g. in SSD}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- H03M 13/29: combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- H03M 13/6312: {Error control coding in combination with data compression}
- H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M 13/37: Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M 13/3776: {using a re-encoding step during the decoding process}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A memory system includes a data channel, a controller configured to output a request across the data channel, and a memory device configured to store data and corresponding first parity, perform a decoding operation on the data to generate second parity in response to receipt of the request across the data channel, generate a difference from the first parity and the second parity, compress the difference, and enable the controller to access the data and the compressed difference to satisfy the request.

## Claims

### Claim 1

A memory system comprising:
a data channel;
a controller configured to output a request across the data channel; and
a memory device configured to store data and corresponding first parity, perform an encoding operation on the data to generate second parity in response to receipt of the request across the data channel, generate a difference from the first parity and the second parity, compress the difference to generate a compressed parity difference, and store the data and the compressed parity difference in a buffer of the memory device,
wherein the controller is configured to retrieve the data and the compressed parity difference from the buffer across the data channel after outputting the request, and generate corrected data using the retrieved data and the retrieved compressed parity difference.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the memory device comprises an error checking and correction (ECC) encoder configured to perform the encoding operation.

### Claim 3 (depends on 1)

The memory system of claim 1, wherein the memory device comprises a subtractor configured to perform a subtraction operation on the first parity and the second parity to generate the difference.

### Claim 4 (depends on 3)

The memory system of claim 3, wherein the subtractor is an XOR logic circuit.

### Claim 5 (depends on 1)

The memory system of claim 1, wherein the memory device comprises a compression circuit and the compress of the difference is performed by the compression circuit.

### Claim 6 (depends on 1)

The memory system of claim 1, wherein the buffer is an input/output (I/O) buffer.

### Claim 7 (depends on 1)

The memory system of claim 1, wherein the controller comprises:
an error checking and correction (ECC) encoder configured to perform an encoding operation on the retrieved data to generate a first result; and
a decompression circuit configured to perform a decompression operation on the retrieved compressed parity difference to generate a second result,
wherein the controller generates the corrected data using the retrieved data, the first result, and the second result.

### Claim 8 (depends on 7)

The memory system of claim 7, the controller further comprising:
a subtractor configured to perform a subtraction operation on the first result and the second result to generate a restored parity; and
an ECC decoder configured to perform a decoding operation on the retrieved data and the restored parity to generate the corrected data.

### Claim 9 (depends on 8)

The memory system of claim 8, wherein the subtractor is an XOR logic circuit.

### Claim 10

A method for controlling a memory system, the method comprising:
loading, by a memory device of the memory system, data and parity in response to receiving a request across a data channel from a controller;
compressing, by the memory device, a difference of the loaded parity and a calculated parity calculated from the loaded data to generate a compressed parity difference;
storing, by the memory device, the loaded data and the compressed parity difference in a buffer of the memory device;
retrieving, by the controller, the loaded data and the compressed parity difference from the buffer across the data channel after outputting the request; and
generating, by the controller, corrected data using the retrieved loaded data and the retrieved compressed parity difference.

### Claim 11 (depends on 10)

The method of claim 10, wherein the compressing comprises:
performing, by the memory device, an encoding operation on the loaded data to generate the calculated parity;
performing, by the memory device, a subtraction operation on the loaded parity and the calculated parity to generate a result; and
compressing, by the memory device, the result to generate the compressed parity difference.

### Claim 12 (depends on 10)

The method of claim 10, wherein the controller generates the corrected data by:
performing an operation on the retrieved compressed parity difference and the retrieved loaded data to generate restored parity; and
performing a decoding operation on the retrieved loaded data and the restored parity to generate the corrected data.

### Claim 13 (depends on 12)

The method of claim 12, wherein the performing of the operation comprises:
performing, by the controller, an encoding operation on the retrieved loaded data to generate a first input;
decompressing, by the controller, the retrieved compressed parity difference to generate a second input; and
performing, by the controller, a subtraction operation on the first input and the second input to generate the restored parity.