# US 10,372,531 B2 · Error-correcting code memory

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,372,531 B2
- Document ID: US10372531B2
- Status: Granted
- Kind: B2
- Application number: 15/653,749
- Filed: 2017-07-19
- Published: 2018-07-05
- Granted: 2019-08-06
- Earliest claimed: 2017-01-05
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Indu Prathapan; Prashanth Saraf; Desmond Pravin Martin Fernandes; Saket Jalan
- Web page: https://patentgrep.com/patent/US10372531B2

## CPC

- G06F 11/1044: {with specific ECC/EDC distribution}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}
- G06F 11/108: {Parity data distribution in semiconductor storages, e.g. in SSD}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- H03M 13/19: Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
- H03M 13/35: Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
- H03M 13/356: {Unequal error protection [UEP]}
- H03M 13/3776: {using a re-encoding step during the decoding process}
- G11C 2207/2263: Write conditionally, e.g. only if new data and old data differ
- G11C 2207/229: Timing of a write operation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

## Claims

### Claim 1

A memory controller comprising:
a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data; and
a write control module that controls the writing of the combined data to the ECC memory.

### Claim 2 (depends on 1)

The memory controller of claim 1, further comprising:
an ECC check and repair module that generates a data repair pattern signal in response to the read data and an error-correcting code;
wherein the ECC memory provides the read data and the error-correcting code to the ECC check and repair module and the read-modify-write logic module.

### Claim 3 (depends on 2)

The memory controller of claim 2, wherein the write control module further comprises:
XOR data logic that executes an XOR (exclusive OR) function on the data repair pattern signal and the combined data to form repaired data that is written to the ECC memory.

### Claim 4 (depends on 3)

The memory controller of claim 3, wherein the XOR function flips a proper subset of bits in the combined data to form the repaired data.

### Claim 5 (depends on 2)

The memory controller of claim 2, wherein the ECC check and repair module receives the read data and the error-correcting code from the ECC memory, and the ECC check and repair module generates an ECC repair pattern signal in response to receipt of the read data and the error-correcting code that is provided to the write control module.

### Claim 6 (depends on 5)

The memory controller of claim 5, further comprising:
an ECC generator that generates a new error-correcting code in response to receipt of the combined data.

### Claim 7 (depends on 6)

The memory controller of claim 6, wherein the write control module further comprises:
XOR ECC logic that executes an XOR (exclusive OR) function on the ECC repair pattern signal and the new error-correcting code from the ECC generator to form a repaired error-correcting code that is written to code memory of the ECC memory.

### Claim 8 (depends on 2)

The memory controller of claim 2, wherein the ECC check and repair module further comprises:
an ECC generator that generates a regenerated error-correcting code in response to receipt of the read data; and
an ECC compare module that compares the regenerated error-correcting code with an error-correcting code provided from the ECC memory and generates an ECC error signal based on the comparison, wherein the ECC error signal is provided to the read-modify-write logic module and the write control module.

### Claim 9 (depends on 8)

The memory controller of claim 8, wherein the memory controller registers the read data, and the read-modify-logic module asserts a stall signal for an additional clock cycle that prevents acceptance of a new memory read or write request in response to the ECC error signal indicating that at least one of bit location of the read data has an error.

### Claim 10 (depends on 8)

The memory controller of claim 8, wherein the write control module further comprises:
XOR data logic that executes an XOR (exclusive OR) function on the data repair pattern signal and the read data to form a repaired data signal; and
a data multiplexer that receives the combined data and the repaired data at respective input nodes and the ECC error signal at a selection node.

### Claim 11 (depends on 10)

The memory controller of claim 10, wherein the data multiplexer writes the combined data to the ECC memory in response to the ECC error signal indicating that no error is present in the read data and the data multiplexer writes the repaired data to the ECC memory in response to the ECC error signal indicating that at least one bit location of the read data has an error.

### Claim 12 (depends on 8)

The memory controller of claim 8, wherein the ECC check and repair module generates a ECC repair pattern signal based on the error-correcting code and the read data, the ECC repair pattern being provided to the write control module and the memory controller further comprises:
another ECC generator that generates a new error-correcting code for the combined data;
wherein the write control module further comprises:
XOR ECC logic that executes an XOR (exclusive OR) function on the ECC repair pattern signal and the new error-correcting code to form a repaired error-correcting code; and
an ECC multiplexer that receives the new error-correcting code and the repaired error-correcting code at respective input nodes and the ECC error signal at a selection node.

### Claim 13 (depends on 12)

The memory controller of claim 12, wherein the ECC multiplexer writes the new error-correcting code to the ECC memory in response to the ECC error signal indicating that no error is detected in the read data and the data multiplexer writes the repaired error-correcting code to the code memory of the ECC memory in response to the ECC error signal indicating that at least one of the read data and the error-correcting code has a detected error.

### Claim 14

A memory controller comprising:
an error-correcting code (ECC) check and repair module that receives read data and an error-correcting code from ECC memory and provides an ECC error signal indicating whether an error is detected in at least one bit location of the read data;
a read-modify-write logic module that receives a partial write data request for partial write data in the ECC memory and combines the partial write data in the partial write data request with the read data provided from the ECC memory to form combined data prior to the ECC check and repair module detecting an error in the at least one bit location of the read data; and
a write control module that controls writing of the combined data to the ECC memory based on the ECC error signal.

### Claim 15 (depends on 14)

The memory controller of claim 14, wherein the memory controller registers the read data and the read-modify-write logic module asserts a stall signal for an extra clock cycle in response to the ECC error signal indicating that an error is detected in at least one bit location of the read data, wherein assertion of the stall signal prevents receipt of subsequent read requests or write requests.

### Claim 16 (depends on 14)

The memory controller of claim 14, wherein the ECC check and repair module further comprises:
an ECC generator that generates a regenerated error-correcting code in response to receipt of the read data; and
an ECC compare module that compares the error-correcting code with the regenerated error-correcting code to generate the ECC error signal and a syndrome signal that identifies a set of bits in the read data and/or the error-correcting code that have an error.

### Claim 17 (depends on 16)

The memory controller of claim 16, wherein the ECC check and repair module further comprises:
a data repair look-up table (LUT) that generates a data repair pattern signal that is provided to the write control in response to the syndrome signal; and
an ECC repair LUT that generates a ECC repair pattern signal that is provided to the write control module in response to the syndrome signal.

### Claim 18

A method comprising:
receiving a partial write data request for data in error-correcting code (ECC) memory;
combining partial write data in the partial write data request with read data provided from a data memory of the ECC memory to form combined data; and
checking the accuracy of the read data in parallel with the combining.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
generating a data repair pattern signal based on the checking; and
generating a ECC repair pattern signal based on the checking.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
generating a new error-correcting code based on the combined data;
executing an XOR (exclusive OR) function on the combined data and the data repair pattern signal; and
executing another XOR function on the new error-correcting code and the ECC repair pattern signal.