# US 10,372,527 B2 · Method of encoding data

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,372,527 B2
- Document ID: US10372527B2
- Status: Granted
- Kind: B2
- Application number: 13/942,315
- Filed: 2013-07-15
- Published: 2015-01-15
- Granted: 2019-08-06
- Earliest claimed: 2013-07-15
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Huimin Chen; Andrew Martwick; Howard Heck; Robert Dunstan; Dennis Bell; Abdul Hawk Ismail
- Web page: https://patentgrep.com/patent/US10372527B2

## CPC

- G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- H03M 5/06: Code representation, e.g. transition, for a given bit cell depending only on the information in that bit cell
- H03M 5/12: Biphase level code, e.g. split phase code, Manchester code; Biphase space or mark code, e.g. double frequency code
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four.

## Claims

### Claim 1

An electronic device, comprising:
an encoder to establish a block header comprising an arrangement of bits, the block header defining at least two block header types, wherein a hamming distance between block header types is at least four;
a transmitter to transmit the block header followed by a block payload, wherein a bit rate clock is embedded in a data stream that comprises the block header and the block payload, and the bit rate clock enables correction of errors in the block header without re-transmission of the block header and the block payload, and in response to a configuration of a single bit a scrambler is bypassed.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein the block header defines more than two block header types.

### Claim 3 (depends on 1)

The electronic device of claim 1, wherein one block header type is a data block header type and another data block header type is a control block header type.

### Claim 4 (depends on 3)

The electronic device of claim 3, wherein the control block is set to 1100 and the data block is set to 0011.

### Claim 5 (depends on 1)

The electronic device of claim 1, wherein the block payload comprises 128 bits and the block header comprises 4 bits.

### Claim 6 (depends on 1)

The electronic device of claim 1, wherein the encoder and transmitter are components of a Universal Serial Bus (USB) implementation.

### Claim 7

An electronic device, comprising:
a receiver to receive line encoded data;
a decoder to identify a block header comprising an arrangement of bits, the block header defining the content of a block payload, the block header defining two block header types, wherein a hamming distance between block header types is at least four; and
a clock recovery circuit, wherein a recovered symbol clock is derived from a recovered bit rate clock resulting in two clock domains and the decoder provides the block header and the block payload to an elastic buffer that operates in the two clock domains, wherein the recovered symbol clock enables block header alignment and block header recovery including error detection and correction.

### Claim 8 (depends on 7)

The electronic device of claim 7, wherein the block header defines more than two block header types.

### Claim 9 (depends on 7)

The electronic device of claim 7, the decoder is to:
detect a single bit error;
report the single bit error to a link layer; and
correct the single bit error.

### Claim 10 (depends on 7)

The electronic device of claim 7, wherein the decoder is to:
detect a double bit error; and
report the double bit error to a link layer.

### Claim 11 (depends on 7)

The electronic device of claim 7, wherein one block header type is a data block header type and another block header type is a control block header type.

### Claim 12 (depends on 11)

The electronic device of claim 11, wherein the control block header is set to 1100 and the data block header is set to 0011.

### Claim 13 (depends on 7)

The electronic device of claim 7, wherein the block payload comprises 128 bits and the block header comprises 4 bits.

### Claim 14 (depends on 7)

The electronic device of claim 7, wherein the decoder and receiver are components of a Universal Serial Bus (USB) implementation.

### Claim 15

A method of encoding data, comprising:
receiving a block payload at a physical layer to be transmitted via a data bus;
establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four; and
deriving a recovered symbol clock from a recovered bit rate clock resulting in two clock domains, wherein the block header and the block payload are received at an elastic buffer that operates in the two clock domains, wherein the recovered symbol clock enables block header alignment and block header recovery including error detection and correction.

### Claim 16 (depends on 15)

The method of claim 15, wherein the block header defines more than two block header types.

### Claim 17 (depends on 15)

The method of claim 15, comprising:
receiving the block payload and the block header transmitted via the data bus at a receiver; and
detecting a single bit error of the block header.

### Claim 18 (depends on 17)

The method of claim 17, comprising:
reporting the single bit error to a link layer; and
correcting the single bit error.

### Claim 19 (depends on 15)

The method of claim 15, comprising:
detecting of a double bit error; and
reporting the double bit error to the link layer.

### Claim 20 (depends on 15)

The method of claim 15, wherein one block header type is a data block header type and another block header type is a control block header type.

### Claim 21 (depends on 20)

The method of claim 20, wherein the control block header is set to 1100 and the data block header is set to 0011.

### Claim 22 (depends on 15)

The method of claim 15, wherein the block payload comprises 128 bits and the block header comprises 4 bits.

### Claim 23 (depends on 15)

The method of claim 15, wherein the block payload is transmitted at a Universal Serial Bus (USB) interface.

### Claim 24

A tangible, non-transitory, computer-readable medium comprising instructions to direct a processor to carry out operations, the operations comprising:
receiving a block payload a physical layer transmitted via a data bus; and
identifying a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four; and
deriving a recovered symbol clock from a recovered bit rate clock resulting in two clock domains, wherein the block header and the block payload are received at an elastic buffer that operates in the two clock domains, wherein the recovered symbol clock enables block header alignment and block header recovery including error detection and correction.

### Claim 25 (depends on 24)

The computer-readable medium of claim 24, wherein the block header defines more than two block header types.