# US 10,372,495 B2 · Circuits and methods providing thread assignment for a multi-core processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,495 B2 - Document ID: US10372495B2 - Status: Granted - Kind: B2 - Application number: 15/435,630 - Filed: 2017-02-17 - Published: 2018-08-23 - Granted: 2019-08-06 - Earliest claimed: 2017-02-17 - Assignees: QUALCOMM Incorporated - Applicants: Qualcomm Incorporated - Inventors: Akash Kumar; Ankita - Web page: https://patentgrep.com/patent/US10372495B2 ## CPC - G06F 9/4893: {taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)} - G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals} - G06F 9/5044: {considering hardware capabilities} - G06F 9/5094: {where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A system includes: a system on chip (SOC) having a plurality of cores; a first memory storing operating parameters for each of the cores; and a second memory storing historical use data for an application, wherein processing threads of the application are assigned to one or more of the plurality of cores based, at least in part, on the operating parameters for each of the cores and the historical use data. ## Claims ### Claim 1 A system comprising: a system on chip (SOC) having a plurality of cores; a first memory storing operating parameters for each of the cores; and a second memory storing historical use data for an application; wherein: processing threads of the application are assigned to one or more of the plurality of cores based, at least in part, on the operating parameters for each of the cores and the historical use data; the operating parameters for each of the cores include a minimum operating voltage for each of the cores; and the processing threads of the application are assigned to one or more of the plurality of cores based, at least in part, by selecting a first core having a minimum operating voltage above an application minimum operating voltage of the historical use data and below a minimum operating voltage associated with a second core. ### Claim 2 (depends on 1) The system of claim 1, wherein the processing threads of the application are assigned to the first core based, at least in part, by selecting the first core for having a minimum operating frequency above an application minimum operating frequency of the historical use data and below a minimum operating frequency associated with a third core. ### Claim 3 (depends on 1) The system of claim 1, wherein the operating parameters include hot spot location data for the plurality of cores, further wherein processing threads of the application are assigned to the first core based, at least in part, on the hot spot location data indicating the first core is further remote from a given hot spot than is a third core. ### Claim 4 (depends on 3) The system of claim 3, wherein the plurality of cores are included in a multi-core central processing unit (CPU), the system further comprising: a graphics processing unit (GPU) on the SOC, wherein the given hot spot is located in the GPU. ### Claim 5 (depends on 1) The system of claim 1, wherein the operating parameters for each of the cores further includes a minimum operating frequency for each of the cores. ### Claim 6 A method comprising: storing in a first memory operating parameters for each of a plurality of cores of a system on chip (SOC); storing in a second memory historical use data for an application; accessing the first memory and the second memory in response to operation of the application; and assigning a plurality of processing threads of the application to one or more of the plurality of cores based, at least in part, on operating parameters of each of the cores and on the historical use data of the application, wherein: the operating parameters for each of the plurality of cores include a minimum operating voltage for each of the cores; and assigning the plurality of processing threads comprises selecting a first core having a minimum operating voltage above an application minimum operating voltage of the historical use data and below a minimum operating voltage associated with a second core of the plurality of cores. ### Claim 7 (depends on 6) The method of claim 6, wherein assigning the plurality of processing threads comprises: selecting the first core for having a minimum operating frequency above an application minimum operating frequency of the historical use data and below a minimum operating frequency associated with a third core of the plurality of cores. ### Claim 8 (depends on 6) The method of claim 6, wherein the historical use data includes a plurality of entries correlating each application with respective thermal gradient information. ### Claim 9 (depends on 8) The method of claim 8, wherein assigning the plurality of processing threads further comprises: placing the processing threads in one or more queues of the first core in response to determining that a thermal gradient of the application is less likely to cause thermal throttling at the first core than at a third core. ### Claim 10 (depends on 6) The method of claim 6, wherein the operating parameters include a plurality of entries correlating each of the cores with respective physical distances to a known hot spot. ### Claim 11 (depends on 10) The method of claim 10, wherein assigning the plurality of processing threads further comprises: placing the processing threads in one or more queues of the first core in response to determining that the first core is a farthest one of the plurality of cores from a known hot spot. ### Claim 12 (depends on 6) The method of claim 6, wherein the plurality of cores are included in a central processing unit (CPU), and wherein the method is performed by an operating system kernel running on the CPU. ### Claim 13 (depends on 6) The method of claim 6, further comprising: updating the historical use data after assigning the processing threads to the first core. ### Claim 14 (depends on 6) The method of claim 6, wherein a frequency of operation of a third core is lower than a frequency of operation of the first core and above a minimum operating frequency of the historical use data, the method further comprising: determining that one or more hardware threads are idle at the third core; and reassigning one or more of the processing threads to the one or more hardware threads at the third core in response to determining that the one or more hardware threads are idle. ### Claim 15 (depends on 6) The method of claim 6, wherein a frequency of operation of a third core is lower than a frequency of operation of the first core and above a minimum operating frequency of the historical use data, and wherein the frequency of operation of the third core is lower than a frequency of operation of a fourth core, the method further comprising: reassigning the processing threads from the first core to the third core and reassigning additional processing threads from the fourth core to the third core; and after reassigning the processing threads and the additional processing threads to the third core, power collapsing the first core and the fourth core. ### Claim 16 (depends on 6) The method of claim 6, wherein the operating parameters for each of the plurality of cores further includes a minimum operating frequency for each of the cores. ### Claim 17 A non-transitory machine-readable medium having stored thereon instructions for performing a method, the medium comprising machine executable code which when executed by at least one processor, causes the at least one processor to: store in a first memory operating parameters for each of a plurality of cores of a system on chip (SOC); store in a second memory historical use data for an application; access the first memory and the second memory in response to operation of the application; and assign a plurality of processing threads of the application to a first core of the plurality of cores based, at least in part, on operating parameters of the first core and on the historical use data of the application, wherein: the operating parameters for each of the plurality of cores include a minimum operating voltage for each of the cores and a minimum operating frequency for each of the cores; and assigning the plurality of processing threads comprises selecting the first core having a minimum operating voltage above an application minimum operating voltage of the historical use data and below a minimum operating voltage associated with a second core of the plurality of cores. ### Claim 18 (depends on 17) The non-transitory machine-readable medium of claim 17, wherein assigning the plurality of processing threads comprises: selecting the first core for having a minimum operating frequency above an application minimum operating frequency of the historical use data and below a minimum operating frequency associated with a third core of the plurality of cores. ### Claim 19 (depends on 17) The non-transitory machine-readable medium of claim 17, wherein the historical use data includes a plurality of entries correlating each of the cores with respective thermal gradient information. ### Claim 20 (depends on 19) The non-transitory machine-readable medium of claim 19, wherein assigning the plurality of processing threads further comprises: placing the processing threads in one or more queues of the first core in response to determining that a thermal gradient of the application is less likely to cause thermal throttling at the first core than at a third core. ### Claim 21 (depends on 17) The non-transitory machine-readable medium of claim 17, wherein a frequency of operation of a third core is lower than a frequency of operation of the first core and above a minimum operating frequency of the historical use data, wherein the medium comprising machine executable code which when executed by the at least one processor, causes the at least one processor to: determine that one or more hardware threads are idle at the third core; and reassign one or more of the processing threads to the one or more hardware threads at the third core in response to determining that the one or more hardware threads are idle. ### Claim 22 (depends on 17) The non-transitory machine-readable medium of claim 17, wherein a frequency of operation of a third core is lower than a frequency of operation of the first core and above a minimum operating frequency of the historical use data, and wherein the frequency of operation of the third core is lower than a frequency of operation of a fourth core, wherein the medium comprising machine executable code which when executed by at the least one processor, causes the at least one processor to: reassign the processing threads from the first core to the third core and reassign additional processing threads from the fourth core to the third core; and after reassigning the processing threads and the additional processing threads to the third core, power collapse the first core and the fourth core. ### Claim 23 A wireless device comprising: a system on chip (SOC) having a plurality of cores; means for storing operating parameters for each of the cores; means for storing historical use data for an application; and means for assigning processing threads of the application to one or more of the plurality of cores based, at least in part, on the operating parameters for each of the cores and the historical use data, wherein: the operating parameters for each of the plurality of cores include a minimum operating voltage for each of the cores; and the processing threads of the application are assigned by the assigning means based, at least in part, by selecting a first core having a minimum operating voltage above an application minimum operating voltage of the historical use data and below a minimum operating voltage associated with a second core. ### Claim 24 (depends on 23) The wireless device of claim 23, wherein the plurality of cores are included in a central processing unit (CPU) on the SOC, and wherein the assigning means comprise an operating system kernel running on the CPU. ### Claim 25 (depends on 23) The wireless device of claim 23, wherein the processing threads of the application are assigned by the assigning means based, at least in part, by selecting the first core for having a minimum operating frequency above an application minimum operating frequency of the historical use data and below a minimum operating frequency associated with a third core. ### Claim 26 (depends on 23) The wireless device of claim 23, wherein the operating parameters for each of the cores further includes a minimum operating frequency for each of the cores. ### Claim 27 A method comprising: storing in a first memory operating parameters for each of a plurality of cores; storing in a second memory historical use data for an application; accessing the first memory and the second memory in response to operation of the application; and assigning a plurality of processing threads of the application to a first core of the plurality of cores based, at least in part, on operating parameters of the first core and on the historical use data of the application, wherein the historical use data includes a plurality of entries correlating each application with respective thermal gradient information. ### Claim 28 (depends on 27) The method of claim 27, wherein assigning the plurality of processing threads further comprises: placing the processing threads in one or more queues of the first core in response to determining that a thermal gradient of the application is less likely to cause thermal throttling at the first core than at a second core. ### Claim 29 A method comprising: storing in a first memory operating parameters for each of a plurality of cores; storing in a second memory historical use data for an application; accessing the first memory and the second memory in response to operation of the application; and assigning a plurality of processing threads of the application to a first core of the plurality of cores based, at least in part, on operating parameters of the first core and on the historical use data of the application, wherein the operating parameters include a plurality of entries correlating each of the cores with respective physical distances to a known hot spot. ### Claim 30 (depends on 29) The method of claim 29, wherein assigning the plurality of processing threads further comprises: placing the processing threads in one or more queues of the first core in response to determining that the first core is a farthest one of the plurality of cores from a known hot spot.