# US 10,372,494 B2 · Thread importance based processor core partitioning > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,494 B2 - Document ID: US10372494B2 - Status: Granted - Kind: B2 - Application number: 15/439,684 - Filed: 2017-02-22 - Published: 2018-05-10 - Granted: 2019-08-06 - Earliest claimed: 2016-11-04 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Mehmet Iyigun; Kai-Lun Hsu; Tristan A. Brown - Web page: https://patentgrep.com/patent/US10372494B2 ## CPC - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 1/08: Clock generators with changeable or programmable clock frequency - G06F 1/324: by lowering clock frequency - G06F 1/3243: {Power saving in microcontroller unit} - G06F 1/329: by task scheduling - G06F 9/4893: {taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)} - G06F 9/5038: {considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups)} - G06F 9/5077: {Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455)} - G06F 9/5094: {where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Each processor core in a device supports various different frequency ranges and/or energy performance preferences, and can operate to run threads at any one of those different frequency ranges and/or energy performance preferences. Processor cores are partitioned into different groups, each group running at different frequency ranges and/or energy performance preferences. Threads in the device are assigned one of multiple importance levels and scheduled to run on a processor core in a particular group based on the importance level of the thread. Lower importance level threads are scheduled to run in a group that is more power efficient, and higher importance level threads are scheduled to run in a group that is higher performance. The group that a processor core is part of can change during operation of the device based on the needs of the device and/or applications running on the device. ## Claims ### Claim 1 A method comprising: configuring a first group of one or more processor cores in a device to run at a first frequency range, the first group associated with a first importance level; configuring a second group of one or more processor cores in the device to run at a second frequency range, the second frequency range including frequencies that are lower than frequencies in the first frequency range, the second group associated with a second importance level; determining an importance level of a first thread scheduled to be executed on the device, the importance level being one of multiple different importance levels; determining, based on the importance level of the first thread, whether the first thread is to be executed on the first group of one or more processor cores or the second group of one or more processor cores; and scheduling the first thread for execution on the determined group of one or more processor cores; dynamically adjusting, during operation of the device, which processor cores of the device are included in the first group of one or more processor cores and which processor cores of the device are included in the second group of one or more processor cores, the dynamically adjusting comprising: comparing a number of threads having the first importance level with a number of threads having the second importance level; and based on the comparing, adjusting at least one processor core in the second group of one or more processor cores to be in the first group of one or more processor cores. ### Claim 2 (depends on 1) The method as recited in claim 1, the importance levels comprising a first importance level and a second importance level, the determining whether the first thread is to be executed on the first group of one or more processor cores or the second group of one or more processor cores comprising determining that the first thread is to be executed on the first group of one or more processor cores in response to determining that the importance level of the first thread is the first importance level, and determining that the first thread is to be executed on the second group of one or more processor cores in response to determining that the importance level of the second thread is the second importance level. ### Claim 3 (depends on 1) The method as recited in claim 1, all of the processor cores in the first group of one or more processor cores and the second group of one or more processor cores comprising homogenous processor cores. ### Claim 4 (depends on 1) The method as recited in claim 1, further comprising dynamically adjusting, during operation of the device, which processor cores of the device are included in the first group of one or more processor cores and which processor cores of the device are included in the second group of one or more processor cores. ### Claim 5 A method comprising: configuring a first group of one or more processor cores in a device to run at a first frequency range, the first group associated with a first importance level; configuring a second group of one or more processor cores in the device to run at a second frequency range, the second frequency range including frequencies that are lower than frequencies in the first frequency range, the second group associated with a second importance level; determining an importance level of a first thread scheduled to be executed on the device, the importance level being one of multiple different importance levels; determining, based on the importance level of the first thread, whether the first thread is to be executed on the first group of one or more processor cores or the second group of one or more processor cores; scheduling the first thread for execution on the determined group of one or more processor cores; and dynamically adjusting, during operation of the device, which processor cores of the device are included in the first group of one or more processor cores and which processor cores of the device are included in the second group of one or more processor cores, the dynamically adjusting comprising: determining whether at least a threshold number of threads having the first importance level are scheduled on the second group of one or more processor cores, and based thereon, either (i) upgrading at least one processor core in the second group to be in the first group, or (ii) downgrading at least one core processor in the first group to be in the second group. ### Claim 6 A method comprising: configuring a first group of one or more processor cores in a device to run at a first frequency range, the first group associated with a first importance level; configuring a second group of one or more processor cores in the device to run at a second frequency range, the second frequency range including frequencies that are lower than frequencies in the first frequency range, the second group associated with a second importance level; determining an importance level of a first thread scheduled to be executed on the device, the importance level of the first thread being one of multiple different importance levels; based on the importance level of the first thread and the importance level of the first group, determining that the first thread is to be executed on the first group of one or more processor cores, and based thereon scheduling the first thread to be executed on the first group; determining that there is not at least one processor core in the first group available to execute the first thread; and in response to determining that there is not at least one processor core in the first group available to execute the first thread: scheduling the first thread for execution on the second group of one or more processor cores; and configuring a processor core in the second group on which the first thread is scheduled for execution to run at a higher frequency range. ### Claim 7 (depends on 6) The method as recited in claim 6, the higher frequency range comprising the first frequency range. ### Claim 8 (depends on 1) The method as recited in claim 1, the frequencies in the second frequency range causing the second group of one or more processor cores to operate more efficiently as determined by performance per watt than the frequencies in the first frequency range cause the first group of one or more processor cores to operate. ### Claim 9 A computing device comprising: multiple processor cores; and a computer-readable storage medium having stored thereon multiple instructions that, responsive to execution by the multiple processor cores, cause the multiple processor cores to perform operations comprising: configuring a first group of the multiple processor cores to run in accordance with a first energy performance preference, each processor core in the first group of processor cores being associated with a first importance level; configuring a second group of the multiple processor cores to run in accordance with a second energy performance preference, each processor core in the second group of processor cores being associated with a second importance level; determining an importance level of a first thread scheduled, or being scheduled, to be executed on the computing device, and based thereon, scheduling the first thread for execution on the first group of multiple processor cores or on the second group of multiple processor cores; dynamically adjusting, during operation of the computing device, which of the multiple processor cores are included in the first group of the multiple processor cores and which of the multiple processor cores are included in the second group of the multiple processor cores; and determining whether at least a threshold number of threads having the first importance level are waiting to be executed, and based thereon, upgrading at least one processor core in the second group to be in the first group. ### Claim 10 (depends on 9) The computing device as recited in claim 9, all of the multiple processor cores comprising a set of homogenous processor cores. ### Claim 11 A computing device comprising: a core configuration module configured to configure a first group of one or more processor cores in the computing device to run at a first frequency, and to configure a second group of one or more processor cores in the computing device to run at a second frequency, the second frequency lower than the first frequency; a thread importance determination module configured to determine an importance level of a first thread scheduled or being scheduled to be executed on the computing device, the importance level being one of multiple different importance levels, wherein the first group is associated with a first importance level and the second group is associated with a second importance level; and a scheduler configured to determine, based on the importance level of the first thread and the importance level associated with the first group, that the first thread is to be executed on the first group, and to schedule the first thread for execution on the determined first group; the scheduler further configured to: determine that there is not at least one processor core in the determined first group available to execute the first thread, and based thereon: schedule the first thread for execution on the second group; and configure a processor core in the second group on which the first thread is scheduled for execution to run at the first frequency. ### Claim 12 (depends on 11) The computing device as recited in claim 11, the processor cores in the first group of one or more processor cores and the second group of one or more processor cores comprising a set of homogenous processor cores. ### Claim 13 (depends on 11) The computing device as recited in claim 11, the core partitioning module and the core configuration module being further configured to dynamically adjust, during operation of the computing device, which processor cores of the computing device are included in the first group of one or more processor cores and which processor cores of the computing device are included in the second group of one or more processor cores. ### Claim 14 (depends on 13) The computing device as recited in claim 13, the first group of one or more processor cores being associated with a first importance level of the multiple importance levels, and the second group of one or more processor cores being associated with a second importance level of the multiple importance levels, the dynamically adjusting comprising: determining whether at least a threshold number of threads having the first importance level are scheduled on the second group of one or more processor cores; and upgrading at least one processor core in the second group of one or more processor cores to being one of the first group of one or more processor cores in response to at least the threshold number of threads having the first importance level being scheduled on the second group of one or more processor cores. ### Claim 15 (depends on 13) The computing device as recited in claim 13, the first group of one or more processor cores being associated with a first importance level of the multiple importance levels, and the second group of one or more processor cores being associated with a second importance level of the multiple importance levels, the dynamically adjusting comprising: determining whether at least a threshold number of threads having the second importance level are scheduled on the first group of one or more processor cores; and downgrading at least one processor core in the first group of one or more processor cores to being one of the second group of one or more processor cores in response to at least the threshold number of threads having the second importance level being scheduled on the first group of one or more processor cores.