# US 10,372,453 B2 · Fetching instructions in an instruction fetch unit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,453 B2 - Document ID: US10372453B2 - Status: Granted - Kind: B2 - Application number: 15/624,121 - Filed: 2017-06-15 - Published: 2017-12-21 - Granted: 2019-08-06 - Earliest claimed: 2016-06-16 - Assignees: MIPS Tech, LLC - Applicants: MIPS Tech, LLC - Inventors: Andrew David Webber; Daniel Ángel Chaver Martínez; Enrique Sedano Algarabel - Web page: https://patentgrep.com/patent/US10372453B2 ## CPC - G06F 9/30047: {Prefetch instructions; cache control instructions} - G06F 9/3009: {Thread control instructions} - G06F 9/30189: {according to execution mode, e.g. mode flag} - G06F 9/3802: {Instruction prefetching} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 12/00: Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method in an instruction fetch unit configured to initiate a fetch of an instruction bundle from a first memory and to initiate a fetch of an instruction bundle from a second memory, wherein a fetch from the second memory takes a predetermined fixed plurality of processor cycles, the method comprising: identifying that an instruction bundle is to be selected for fetching from the second memory in a predetermined future processor cycle; and initiating a fetch of the identified instruction bundle from the second memory a number of processor cycles prior to the predetermined future processor cycle based upon the predetermined fixed plurality of processor cycles taken to fetch from the second memory. ## Claims ### Claim 1 A method in an instruction fetch unit configured to initiate a fetch of an instruction bundle from a first memory and to initiate a fetch of an instruction bundle from a second memory, wherein a fetch from the second memory takes a predetermined fixed plurality of processor cycles, the method comprising: identifying that an instruction bundle is to be selected for fetching from the second memory in a predetermined future processor cycle based on a prediction, wherein the prediction comprises: predicting a thread to be selected in a predetermined future processor cycle; determining a mode for the predicted thread; and selecting the next fetch address for the predicted thread; allocating a thread to a first mode if it is determined that an instruction bundle associated with that thread is to be fetched from the first memory or allocating the thread to a second mode if it is determined that the instruction bundle associated with that thread is to be fetched from the second memory; and initiating a fetch of the identified instruction bundle from the second memory a number of processor cycles prior to the predetermined future processor cycle based upon the predetermined fixed plurality of processor cycles taken to fetch from the second memory. ### Claim 2 (depends on 1) The method according to claim 1, further comprising performing the fetch of the identified instruction bundle from the second memory in parallel with another memory access. ### Claim 3 (depends on 1) The method according to claim 1, wherein identifying that an instruction bundle is to be fetched from a second memory comprises determining whether a memory address of the instruction bundle is within a range of memory addresses in the second memory. ### Claim 4 (depends on 1) The method according to claim 1, wherein a fetch from the first memory takes one processor cycle and wherein the time taken between selecting an instruction bundle for fetching from the first memory and issuing the fetched instruction bundle is the fetch latency, wherein initiating a fetch of the identified instruction bundle from the second memory prior to the predetermined future processor cycle is further based upon the duration of the fetch latency. ### Claim 5 (depends on 1) The method according to claim 1, further comprising, each processor cycle, selecting an instruction bundle to be fetched. ### Claim 6 (depends on 5) The method according to claim 5, wherein selecting an instruction bundle to be fetched each processor cycle is performed based upon a round-robin schedule. ### Claim 7 (depends on 1) The method according to claim 1, wherein instruction bundles to be fetched are each associated with one of a plurality of threads. ### Claim 8 (depends on 1) The method according to claim 1, wherein predicting which bundle is to be selected for fetching in a predetermined future processor cycle comprises predicting which thread of a plurality threads is to be selected for fetching. ### Claim 9 (depends on 8) The method according to claim 8, wherein predicting which instruction bundle is to be selected for fetching in a predetermined future processor cycle is based upon predicting which thread will be selected according to a round-robin schedule. ### Claim 10 (depends on 8) The method according to claim 8, further comprising: associating a flag with each thread, the flag indicating that the thread is either fetchable or unfetchable; and predicting a thread to be selected based upon threads that are flagged as fetchable. ### Claim 11 (depends on 8) The method according to claim 8, further comprising: flagging a thread as unfetchable due to at least one of a cache miss, a Translation Lookaside Buffer (TLB) miss, a buffer for execution being full, or a busy second memory bank; or flagging a thread as fetchable due to the buffer for execution no longer being full, a stabilized thread, a free second memory bank, a restart of a thread, or due to cache or TLB miss handling being finished. ### Claim 12 (depends on 1) The method according to claim 1, further comprising identifying, in a future processor cycle, that the predicted instruction bundle was not selected for fetching and (i) halting the fetch of the predicted instruction bundle from the second memory; or selecting the predicted instruction bundle for fetching in place of the instruction bundle actually selected at the future predetermined processor cycle. ### Claim 13 (depends on 1) The method according to claim 1, further comprising identifying that a thread in the first mode requires a fetch from the second memory and changing the mode of the thread from the first mode to the second mode. ### Claim 14 (depends on 1) The method according to claim 1, further comprising identifying that a thread in the second mode requires a fetch from the first memory and changing the mode of the thread from the second mode to the first mode. ### Claim 15 (depends on 1) The method according to claim 1, wherein the first memory is an instruction cache and wherein the second memory is an Instruction Scratchpad Random-Access-Memory (ISPRAM). ### Claim 16 An instruction fetch unit configured to initiate a fetch of an instruction bundle from a first memory and to initiate a fetch of an instruction bundle from a second memory, and wherein a fetch from the second memory takes a predetermined fixed number of processor cycles, the instruction fetch unit comprising: a control module configured to: identify that an instruction bundle is to be selected for fetching from the second memory in a predetermined future processor cycle based on a prediction, wherein the prediction comprises: predicting a thread to be selected in a predetermined future processor cycle; determining a mode for the predicted thread; and selecting the next fetch address for the predicted thread; allocate a thread to a first mode if it is determined that an instruction bundle associated with that thread is to be fetched from the first memory or allocating the thread to a second mode if it is determined that the instruction bundle associated with that thread is to be fetched from the second memory; and initiate a fetch of the identified instruction bundle from the second memory a number of processor cycles prior to the predetermined future processor cycle based upon the predetermined fixed plurality of processor cycles taken to fetch from the second memory. ### Claim 17 A computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an instruction fetch unit configured to initiate a fetch of an instruction bundle from a first memory and to initiate a fetch of an instruction bundle from a second memory, and wherein a fetch from the second memory takes a predetermined fixed plurality of processor cycles, wherein the instruction fetch unit comprises a control module configured to: identify that an instruction bundle is to be selected for fetching from the second memory in a predetermined future processor cycle based on a prediction, wherein the prediction comprises: predicting a thread to be selected in a predetermined future processor cycle; determining a mode for the predicted thread; and selecting the next fetch address for the predicted thread; allocate a thread to a first mode if it is determined that an instruction bundle associated with that thread is to be fetched from the first memory or allocating the thread to a second mode if it is determined that the instruction bundle associated with that thread is to be fetched from the second memory; and initiate a fetch of the identified instruction bundle from the second memory a number of processor cycles prior to the predetermined future processor cycle based upon the predetermined fixed plurality of processor cycles taken to fetch from the second memory.