# US 10,372,450 B2 · Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,450 B2 - Document ID: US10372450B2 - Status: Granted - Kind: B2 - Application number: 15/647,123 - Filed: 2017-07-11 - Published: 2018-03-08 - Granted: 2019-08-06 - Earliest claimed: 2017-07-11 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Victor W. Lee; Daehyun Kim; Tin-Fook Ngai; Jayashankar Bharadwaj; Albert Hartono; Sara Baghsorkhi; Nalini Vasudevan - Web page: https://patentgrep.com/patent/US10372450B2 ## CPC - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30018: {Bit or string instructions} - G06F 9/30021: {Compare instructions, e.g. Greater-Than, Equal-To, MINMAX} - G06F 9/30038: {using a mask} - G06F 9/30072: {to perform conditional operations, e.g. using predicates or guards} - G06F 9/30025: {Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion} - G06F 15/8007: {single instruction multiple data [SIMD] multiprocessors} - G06F 15/8053: {Vector processors} - G06F 15/8084: {Special arrangements thereof, e.g. mask or switch} - G06F 15/8092: {Array of vector units} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described. ## Claims ### Claim 1 A method of performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction that includes at least a source writemask register operand, a destination writemask register operand, and an opcode, the method comprising: decoding the single instruction; executing the decoded single instruction to determine a least significant bit position of the source writemask register that is a true value; storing a true value only in each bit position of the destination writemask register that is lesser significance than the determined corresponding least significant bit position. ### Claim 2 (depends on 1) The method of claim 1, further comprising: storing a false value in each bit position of the destination writemask register that is of equal or greater significance than the determined corresponding bit position. ### Claim 3 (depends on 1) The method of claim 1, further comprising: storing a true value in a bit position of the destination writemask register that is of equal significance to the determined corresponding bit position. ### Claim 4 (depends on 3) The method of claim 3, wherein the instruction further includes a control writemask operand and to determine a least significant bit position of the source writemask register that is a true value further comprises determining that a value in the control writemask register at that bit position is also true. ### Claim 5 (depends on 1) The method of claim 1, wherein the instruction further includes a control writemask operand and to determine a least significant bit position of the source writemask register that is a true value further comprises determining that a value in the control writemask register at that bit position is also true. ### Claim 6 (depends on 1) The method of claim 1, wherein the registers are 16-bit registers. ### Claim 7 (depends on 1) The method of claim 1, wherein the registers are 64-bit registers. ### Claim 8 An article of manufacture comprising: a non-transitory tangible machine-readable storage medium having stored thereon an occurrence of an instruction, wherein the instruction's format specifies as its source operand a writemask register and specifies as its destination a single writemask register, and wherein the instruction format includes an opcode which instructs a machine, responsive to the single occurrence of the single instruction, to cause a determination of a least significant bit position of the source writemask register that is a true value and storage of a true only value in each bit position of the destination writemask register that is lesser significance than the determined corresponding least significant bit position. ### Claim 9 (depends on 8) The article of manufacture of claim 8, further comprising: storage of a false value in each bit position of the destination writemask register that is of equal or greater significance than the determined corresponding bit position. ### Claim 10 (depends on 8) The article of manufacture of claim 8, further comprising: storage of a true value in a bit position of the destination writemask register that is of equal significance to the determined corresponding bit position. ### Claim 11 (depends on 10) The article of manufacture of claim 10, wherein the instruction further includes a control writemask operand and to determine a least significant bit position of the source writemask register that is a true value further comprises determining that a value in the control writemask register at that bit position is also true. ### Claim 12 (depends on 8) The article of manufacture of claim 8, wherein the instruction further includes a control writemask operand and to determine a least significant bit position of the source writemask register that is a true value further comprises determining that a value in the control writemask register at that bit position is also true. ### Claim 13 (depends on 8) The article of manufacture of claim 8, wherein the registers are 16-bit registers. ### Claim 14 (depends on 8) The article of manufacture of claim 8, wherein the registers are 64-bit registers. ### Claim 15 An apparatus comprising; a hardware decoder to decode a generation of a predicate mask based on vector comparison instruction that includes at least a source writemask register operand, a destination writemask register operand, and an opcode; execution circuitry to determine a least significant bit position of the source writemask register that is a true value and store a true value only in each bit position of the destination writemask register that is lesser significance than the determined corresponding least significant bit position. ### Claim 16 (depends on 15) The apparatus of claim 15, further comprising: the execution circuitry to store a false value in each bit position of the destination writemask register that is of equal or greater significance than the determined corresponding bit position. ### Claim 17 (depends on 15) The apparatus of claim 15, further comprising: the execution circuitry to store a true value in a bit position of the destination writemask register that is of equal significance to the determined corresponding bit position. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the instruction further includes a control writemask operand and the execution circuitry to determine a least significant bit position of the source writemask register that is a true value further comprises determining that a value in the control writemask register at that bit position is also true. ### Claim 19 (depends on 15) The apparatus of claim 15, wherein the instruction further includes a control writemask operand and the execution circuitry to determine a least significant bit position of the source writemask register that is a true value further comprises determining that a value in the control writemask register at that bit position is also true. ### Claim 20 (depends on 15) The apparatus of claim 15, wherein the registers are 16-bit registers.