# US 10,372,415 B2 · Internally truncated multiplier > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,415 B2 - Document ID: US10372415B2 - Status: Granted - Kind: B2 - Application number: 15/587,096 - Filed: 2017-05-04 - Published: 2017-11-09 - Granted: 2019-08-06 - Earliest claimed: 2016-05-04 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Jawaharlal Tangudu; Suvam Nandi; Pooja Sundar; Jaiganesh Balakrishnan - Web page: https://patentgrep.com/patent/US10372415B2 ## CPC - G06F 7/523: Multiplying only - G06F 7/50: Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) - H03D 7/161: {all the frequency changers being connected in cascade} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03D: DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER (masers, lasers H01S; circuits capable of acting both as modulator and demodulator H03C; details applicable to both modulators and frequency-changers H03C; demodulating pulses H03K9/00; transforming types of pulse modulation H03K11/00; coding, decoding or code conversion, in general H03M; repeater stations H04B7/14; demodulators adapted for AC systems of digital information transmission H04L27/00; synchronous demodulators adapted for colour television H04N9/66) ## Abstract A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit. ## Claims ### Claim 1 A multiplier circuit, comprising: a partial product generation circuit configured to generate a plurality of partial products for a multiplier and a multiplicand; a truncation circuit coupled to the partial product generation circuit, the truncation circuit configured to shorten at least some partial products of the plurality of partial products, by removing a least significant bit from the at least some of the partial products, to generate truncated partial products; a summation circuit coupled to the truncation circuit, the summation circuit configured to sum the truncated partial products, to generate a multiplication product; and a bias compensation circuit coupled to the summation circuit, the bias compensation circuit configured to generate a bias compensation value based on whether the multiplier and the multiplicand are random. ### Claim 2 (depends on 1) The multiplier circuit of claim 1, wherein the bias compensation circuit is further configured to: determine a bias introduced by the truncation circuit; and generate the bias compensation value based on the bias. ### Claim 3 (depends on 1) The multiplier circuit of claim 1, wherein the summation circuit is further configured to add the bias compensation value to a sum of the truncated partial products. ### Claim 4 (depends on 1) The multiplier circuit of claim 1, wherein the bias compensation circuit is configured to generate the bias compensation value based on a number of the partial products truncated by the truncation circuit. ### Claim 5 (depends on 4) The multiplier circuit of claim 4, wherein the bias compensation circuit is configured to increment the bias compensation value for each of the partial products that is truncated by the truncation circuit. ### Claim 6 (depends on 1) The multiplier circuit of claim 1, wherein the bias compensation circuit is configured to generate the bias compensation value as a constant value. ### Claim 7 (depends on 6) The multiplier circuit of claim 6, wherein the bias compensation circuit is configured to generate the constant value in response to determining that the multiplier and the multiplicand are statistically random. ### Claim 8 (depends on 1) The multiplier circuit of claim 1, wherein the bias compensation circuit is configured to compute the bias compensation value based on a number of nonzero bits of the multiplier. ### Claim 9 (depends on 8) The multiplier circuit of claim 8, wherein the bias compensation circuit is configured to compute the bias compensation value to be half the number of nonzero bits of the multiplier. ### Claim 10 A digital down converter (DDC), comprising: a mixer configured to multiply samples of a radio frequency signal with samples of a down conversion frequency, to produce an intermediate frequency signal, the mixer comprising: a multiplier to multiply the samples of the radio frequency signal with the samples of the down conversion frequency, the multiplier comprising: a partial product generation circuit configured to generate a plurality of partial products for multiplying a sample of the radio frequency signal and a sample of the down conversion frequency; a truncation circuit coupled to the partial product generation circuit, the truncation circuit configured to shorten at least some of the partial products by removing a least significant bit from the at least some of partial products, to generate truncated partial products; a summation circuit coupled to the truncation circuit, the summation circuit configured to sum the truncated partial products produced by the truncation circuit, to generate a multiplication product; and a bias compensation circuit coupled to the summation circuit, the bias compensation circuit configured to generate a bias compensation value based on whether the sample of the radio frequency signal and the sample of the down conversion frequency are random. ### Claim 11 (depends on 10) The DDC of claim 10, wherein the bias compensation circuit is further configured to: determine a bias introduced by the truncation circuit; and generate the bias compensation value based on the bias. ### Claim 12 (depends on 10) The DDC of claim 10, wherein the summation circuit is further configured to add the bias compensation value to a sum of the truncated partial products. ### Claim 13 (depends on 10) The DDC of claim 10, wherein the bias compensation circuit is configured to generate the bias compensation value based on a number of the partial products truncated by the truncation circuit. ### Claim 14 (depends on 13) The DDC of claim 13, wherein the bias compensation circuit is configured to increment the bias compensation value for each of the partial products that are truncated by the truncation circuit. ### Claim 15 (depends on 10) The DDC of claim 10, wherein the bias compensation circuit is configured to generate the bias compensation value as a constant value. ### Claim 16 (depends on 15) The DDC of claim 15, wherein the bias compensation circuit is configured to generate the constant value in response to determining that the samples of the radio frequency signal and the samples of the down conversion frequency are statistically random. ### Claim 17 (depends on 10) The DDC of claim 10, wherein the bias compensation circuit is configured to generate the bias compensation value based on a number of non-zero least significant bits of either the samples of the radio frequency signal or the samples of the down conversion frequency. ### Claim 18 A method for multiplication, the method comprising: generating, by a partial product generation circuit, a plurality of partial products for a multiplier and a multiplicand; shortening, by a truncation circuit, at least some partial products of the plurality of partial products by removing a least significant bit from the at least some of the partial products, to generate truncated partial products; summing, by a summation circuit, the truncated partial products, to generate a multiplication product; and generating, by a bias compensation circuit, a bias compensation value based on whether the multiplier and the multiplicand are random. ### Claim 19 (depends on 18) The method of claim 18, further comprising adding, by the summation circuit, the bias compensation value to a sum of the truncated partial products. ### Claim 20 (depends on 18) The method of claim 18, wherein generating the bias compensation value is performed based on a number of the partial products truncated by the truncation circuit.