# US 10,372,382 B2 · Methods and apparatus for read disturb detection based on logical domain

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- Number: US 10,372,382 B2
- Document ID: US10372382B2
- Status: Granted
- Kind: B2
- Application number: 15/394,560
- Filed: 2016-12-29
- Published: 2018-07-05
- Granted: 2019-08-06
- Earliest claimed: 2016-12-29
- Assignees: Western Digital Technologies, Inc.
- Applicants: Western Digital Technologies, Inc.
- Inventors: Parvaneh Alavi; Hung-min Chang; Haining Liu; Jerry Lo; Hung-Cheng Yeh
- Web page: https://patentgrep.com/patent/US10372382B2

## CPC

- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/0616: {in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]}
- G06F 3/064: {Management of blocks}
- G06F 11/004: {Error avoidance (G06F11/07 and subgroups take precedence)}
- G06F 11/3034: {where the computing system component is a storage system, e.g. DASD based or network based (digital input from or digital output to record carriers G06F3/06; digital recording or reproducing G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)}
- G06F 11/3037: {where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 16/3431: {Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step}
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G06F 11/3409: {for performance assessment}
- G06F 11/3471: {Address tracing}
- G06F 2201/81: Threshold
- G06F 2201/88: Monitoring involving counting
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Aspects of the disclosure provide methods and apparatus that monitor and mitigate Read Disturb errors in non-volatile memory (NVM) devices such as NAND flash memories. The disclosed methods and apparatus determine which logical block addresses (LBAs) in the NVM device are frequently accessed by a host, rather than looking a physical address accesses. The potential Read Disturb errors may then be mitigated by triggering Read Disturb mitigation when the numbers of access of one or more of the frequently accessed LBAs exceeds a predefined number of accesses.

## Claims

### Claim 1

A method of monitoring a non-volatile memory (NVM) for potential Read Disturb errors, the method comprising:
maintaining a data structure of a plurality of logical block addresses respectively corresponding to physical memory address locations of the NVM, wherein the data structure further includes read access counts corresponding to a number of times the plurality of logical block addresses has been read accessed by a host, and wherein adjacent logical block addresses correspond to at least some non-adjacent physical memory address locations in the NVM; and
comparing the read access counts of the plurality of logical block addresses to a predefined threshold number of access counts to determine whether to trigger a Read Disturb mitigation for the physical memory address locations of the NVM corresponding to the plurality of logical block addresses.

### Claim 2 (depends on 1)

The method of claim 1, wherein maintaining the data structure of the plurality of logical block addresses further comprises including only logical block addresses in the data structure that have a read access count greater than a predefined minimum number of accesses.

### Claim 3 (depends on 1)

The method of claim 1, wherein the data structure is configured as a data tree structure wherein each node in the tree represents a logical memory location accessed by the host, and each node includes data including one or more of a logical block address, an access count of the logical block address, an index of a next logical block address location in the data tree structure, and an index of a previous logical block address location in the data tree structure.

### Claim 4 (depends on 1)

The method of claim 1, wherein the data structure is stored in a local memory of a solid state drive (SSD) including the NVM, and the local memory is coupled to a controller configured to control accesses to the NVM.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
updating a Read Disturb table stored in the NVM with access count values of physical memory locations corresponding to the plurality of logical block addresses maintained in the data structure.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
maintaining a low access list of logical block addresses accessed by the host within a range of access counts, wherein a maximum of the range is less than a predefined minimum number of accesses required for inclusion of a logical block address in the data structure.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
updating a Read Disturb table stored in the NVM with access count values of physical memory locations corresponding to the logical block addresses maintained in the low access list of logical block addresses.

### Claim 8 (depends on 1)

The method of claim 1, further comprising performing Read Disturb mitigation for the physical memory address locations of the NVM corresponding to the plurality of logical block addresses based on the comparison of the read access counts to the predefined threshold number of access counts.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
detecting a trend in a host access pattern based on the data structure;
determining whether to trigger the Read Disturb mitigation based on the detected trend in the host access pattern; and
performing the Read Disturb mitigation based on the detected trend.

### Claim 10 (depends on 1)

The method of claim 1, further comprising performing the Read Disturb mitigation by directing logical block addresses having read access counts exceeding the threshold number to a same physical block of the NVM.

### Claim 11

A solid state drive (SSD) comprising:
a non-volatile memory (NVM); and
a controller communicatively coupled to a host device, a local memory device, and the NVM,
wherein the controller is configured to:
store read access counts in the local memory device, wherein the read access counts correspond to a number of times logical block addresses are read accessed by the host device, wherein the logical block addresses respectively correspond to physical memory address locations of the NVM, and wherein adjacent logical block addresses correspond to at least some non-adjacent physical memory address locations in the NVM;
determine when one or more of the stored read access counts of the logical block addresses exceed a predefined threshold number of access counts; and
trigger a Read Disturb prevention process for physical memory address locations in the NVM corresponding to a logical block address having corresponding read access counts determined to exceed the predefined threshold number of access counts.

### Claim 12 (depends on 11)

The solid state drive of claim 11, wherein the controller is further configured to:
store the read access counts in a tree data structure having a plurality of nodes each corresponding to a respective logical block address.

### Claim 13 (depends on 12)

The solid state drive of claim 12, wherein the controller is further configured to:
store only logical block addresses in the data structure having a read access count greater than a predefined minimum number of accesses.

### Claim 14 (depends on 11)

The solid state drive of claim 11, wherein the controller is further configured to:
update a Read Disturb table stored in the NVM with the stored access count values.

### Claim 15 (depends on 11)

The solid state drive of claim 11, wherein the controller is further configured to:
update a Read Disturb table stored in the NVM with access count values of the physical memory locations corresponding to the logical block addresses stored in the local memory.

### Claim 16 (depends on 11)

The solid state drive of claim 11, wherein the controller is further configured to:
store a low access list of logical block addresses in the local memory device, wherein the low access list comprises logical block addresses in the NVM accessed by the host device within a range of access counts, wherein a maximum of the range is less than a predefined minimum number of accesses required for inclusion of a logical block address in the data structure.

### Claim 17 (depends on 11)

The SSD of claim 11, wherein the controller is further configured to sort and group of NVM read access accesses into a matrix that groups the accesses into a higher risk pool of addresses and a lesser risk pool of addresses.

### Claim 18 (depends on 11)

The SSD of claim 11, wherein the controller is further configured to:
detect a trend in a host access pattern based on the data structure;
determine whether to trigger the Read Disturb mitigation based on the detected trend in the host access pattern; and
perform the Read Disturb mitigation based on the detected trend.

### Claim 19 (depends on 12)

The SSD of claim 12, wherein the controller is further configured to perform the Read Disturb mitigation to relocate pages within the NVM based on the tree data structure to reduce write amplification.

### Claim 20

An apparatus for mitigating Read Disturb errors in a non-volatile memory (NVM), the apparatus comprising:
means for determining which logical block addresses (LBAs) of a host are frequently accessed by the host, wherein the LBAs respectively correspond to physical memory address locations of the NVM, wherein adjacent LBAs correspond to at least some non-adjacent physical memory address locations in the NVM, and wherein the means for determining further comprises means for determining a number of times the LBAs have been read accessed by the host; and
means for triggering a Read Disturb prevention process when a read access count of one or more of the LBAs exceeds a predefined number of accesses.

### Claim 21 (depends on 20)

The apparatus of claim 20, further comprising:
means for maintaining the LBAs in the NVM that are frequently accessed by the host in a data structure of a plurality of logical block addresses of the NVM where the data structure further includes read access counts for each of the logical block addresses of the plurality of logical block addresses maintained in the data structure.