# US 10,372,377 B2 · Memory controller, memory system, and control method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,377 B2 - Document ID: US10372377B2 - Status: Granted - Kind: B2 - Application number: 15/691,711 - Filed: 2017-08-30 - Published: 2018-09-27 - Granted: 2019-08-06 - Earliest claimed: 2017-03-22 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Katsuhiko Iwai - Web page: https://patentgrep.com/patent/US10372377B2 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 3/0658: {Controller construction arrangements} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 12/04: Addressing variable-length words or parts of words - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory controller includes a memory interface that is connected to a non-volatile memory that includes a plurality of memory cells, and a control unit. The control unit controls the memory interface to perform writing of data that has a first number of bits to a first memory cell in an n-bit write mode (where n is 2 or more), and when performing reading of the data written into the first memory cell, to control the memory interface to perform reading of data in an m-bit read mode (where m is less than n), as a result of which data that has a second number of bits which is smaller than the first number of bits, is returned from the first memory cell. ## Claims ### Claim 1 A memory controller comprising: a memory interface that is connectable to a nonvolatile memory that includes a plurality of memory cells; a memory including a mode management table indicating, as an operation mode for a group of memory cells including a first memory cell, an n-bit mode (where n is 2 or more) or an m-bit mode (where m is less than n); and a processor configured to: during a write operation, control the memory interface to perform writing of data that has a first number of bits to the first memory cell in the n-bit mode, when the mode management table indicates the n-bit mode as the operation mode, and operate to convert data that has a second number of bits less than the first number into data that has the first number of bits by addition of dummy data and control the memory interface to perform writing of the converted data to the first memory cell in the n-bit mode, when the mode management table indicates the m-bit mode as the operation mode, and during a read operation, control the memory interface to perform reading of data in the first memory cell in the m-bit mode, when the mode management table indicates the m-bit mode as the operation mode. ### Claim 2 (depends on 1) The memory controller according to claim 1, wherein the data that has the first number of bits is two-bit data that includes a high order bit and a low order bit, and wherein the dummy data is added as a high order bit of the data that has the second number of bits or as a lower order bit of the data that has the second number of bits. ### Claim 3 (depends on 2) The memory controller according to claim 2, wherein when the mode management table indicates the m-bit mode as the operation mode, the first memory cell is programmed into one of only two of four threshold voltage distributions that are achievable with writing in the n-bit mode during the write operation. ### Claim 4 (depends on 3) The memory controller according to claim 3, wherein the two threshold voltage distributions into which the first memory cell is programmed, are non-adjacent threshold voltage distributions among the four threshold voltage distributions that are achievable with writing in the n-bit mode. ### Claim 5 (depends on 1) The memory controller according to claim 1, wherein the group of memory cells is a page of memory cells and an entry of the mode management table corresponding to the page of memory cells indicates a total number of times reading has been carried out with respect to the page of memory cells, the total number being greater than a threshold number. ### Claim 6 (depends on 1) The memory controller according to claim 1, wherein the group of memory cells is a block of memory cells and an entry of the mode management table corresponding to the block of memory cells indicates a total number of times reading has been carried out with respect to the block of memory cells, the total number being greater than a threshold number. ### Claim 7 A method of performing read and write operations on a nonvolatile memory that includes a plurality of memory cells, said method comprising: during a write operation, performing writing of data that has a first number of bits to a first memory cell in an n-bit mode (where n is 2 or more), when a mode management table indicating, as an operation mode for a group of memory cells including the first memory cell, the n-bit mode; and converting data that has a second number of bits less than the first number into data that has the first number of bits by adding dummy data, and performing writing of the converted data to the first memory cell in the n-bit mode, when the mode management table indicates, as the operation mode, an m-bit mode (where m is less than n); and during a read operation, performing reading of data in the first memory cell in the m-bit mode, when the mode management table indicates the m-bit mode as the operation mode. ### Claim 8 (depends on 1) The memory controller according to claim 1, wherein the processor is further configured to periodically determine whether or not a predetermined degree of read disturbance is caused on the group of memory cells, and update the operation mode in the mode management table based on a determination result of whether or not the predetermined degree of read disturbance is caused on the group of memory cells. ### Claim 9 (depends on 8) The memory controller according to claim 8, wherein the processor is further configured to determine whether or not the predetermined degree of read disturbance is caused on the group of memory cells at least based on a number of times reading has been carried out with respect to the group of memory cells. ### Claim 10 (depends on 8) The memory controller according to claim 8, wherein the processor is further configured to determine whether or not the predetermined degree of read disturbance is caused on the group of memory cells at least based on writing of a test pattern. ### Claim 11 (depends on 1) The memory controller according to claim 1, wherein during the read operation, the processor is further configured to control the memory interface to perform reading of data in the first memory cell in the n-bit mode, when the mode management table indicates the m-bit mode as the operation mode. ### Claim 12 A memory system comprising: a nonvolatile memory that includes a plurality of memory cells; and a memory controller including: a memory interface connectable to the nonvolatile memory; a memory including a mode management table indicating, as an operation mode for a group of memory cells including a first memory cell, an n-bit mode (where n is 2 or more) or an m-bit mode (where m is less than n); and a processor configured to: during a write operation, control the memory interface to perform writing of data that has a first number of bits to the first memory cell in the n-bit mode, when the mode management table indicates the n-bit mode as the operation mode, and operate to convert data that has a second number of bits less than the first number into data that has the first number of bits by addition of dummy data and control the memory interface to perform writing of the converted data to the first memory cell in the n-bit mode, when the mode management table indicates the m-bit mode as the operation mode, and during a read operation, control the memory interface to perform reading of data in the first memory cell in the m-bit mode, when the mode management table indicates the m-bit mode as the operation mode. ### Claim 13 (depends on 12) The memory controller according to claim 12, wherein the group of memory cells is a page of memory cells and an entry of the mode management table corresponding to the page of memory cells indicates a total number of times reading has been carried out with respect to the page of memory cells, the total number being greater than a threshold number. ### Claim 14 (depends on 12) The memory controller according to claim 12, wherein the group of memory cells is a block of memory cells and an entry of the mode management table corresponding to the block of memory cells indicates a total number of times reading has been carried out with respect to the block of memory cells, the total number being greater than a threshold number. ### Claim 15 (depends on 7) The method according to claim 7, wherein when the mode management table indicates the m-bit mode as the operation mode, the first memory cell is programmed into one of only two of four or more threshold voltage distributions that are achievable with writing in the n-bit mode during the write operation. ### Claim 16 (depends on 7) The method according to claim 7, wherein the data that has the first number of bits is two-bit data that includes a high order bit and a low order bit, and the dummy data is added as a high order bit of the data that has the second number of bits or as a lower order bit of the data that has the second number of bits.