# US 10,372,369 B2 · Apparatuses and methods for single level cell caching

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- Number: US 10,372,369 B2
- Document ID: US10372369B2
- Status: Granted
- Kind: B2
- Application number: 16/101,951
- Filed: 2018-08-13
- Published: 2018-12-06
- Granted: 2019-08-06
- Earliest claimed: 2016-10-27
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Daniel Doyle
- Web page: https://patentgrep.com/patent/US10372369B2

## CPC

- G06F 3/0644: {Management of space entities, e.g. partitions, extents, pools}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0635: {by changing the path, e.g. traffic rerouting, path reconfiguration}
- G06F 3/064: {Management of blocks}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0685: {Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/5635: {Erasing circuits}
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 16/10: Programming or data input circuits
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 2211/562: Multilevel memory programming aspects
- G11C 2211/5641: Multilevel memory having cells with different number of storage levels
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.

## Claims

### Claim 1

A method comprising:
receiving, at a control circuit, a first set of write data;
determining whether the first set of write data is to be stored in a lower page or an upper page of a block of multilevel memory cells;
responsive to determining that the first set of write data is to be stored in the lower page, storing the first set of write data in a page of a block of single level memory cells and the lower page of the block of multilevel memory cells; and
responsive to determining that the first set of write data is to be stored in the upper page, storing the first set of write data directly in the upper page of the block of multilevel memory cells without storing the first set of write data in the page of the block of single level memory cells.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
storing a plurality of sets of write data to lower pages of the block of multilevel memory cells prior to storing the first set of write data in the upper page of the block of multilevel memory cells.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
receiving, at the control circuit, a second set of write data; and
responsive to storing the first set of write data in the lower page of the block of multilevel memory cells, storing the second set of write data in the upper page of the block of multilevel memory cells.

### Claim 4 (depends on 1)

The method of claim 1, wherein the multilevel memory cells comprise memory cells configured to store at least three bits.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
responsive to storing the first set of write data in the upper page of the block of memory cells, erasing the block of single level memory cells.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
providing a confirmation message responsive to storing the first set of write data in the page of the block of single level memory cells.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
updating a page map responsive to storing the first set of write data in one of the lower page and the upper page of the block of multilevel memory cells.

### Claim 8 (depends on 3)

The method of claim 3, further comprising detecting a power loss event prior to completing storing the second set of write data in the upper page of the block of multilevel memory cells.

### Claim 9 (depends on 8)

The method of claim 8, further comprising copying the first set of write data from the page of the block of single level memory cells to the lower page of the block of multilevel memory cells.

### Claim 10 (depends on 9)

The method of claim 9, reinitiating storing the second set of write data in the upper page of the block of multilevel memory cells.

### Claim 11 (depends on 10)

The method of claim 10, further comprising erasing the page of the block of single level memory cells responsive to completing the storing of the second set of write data in the upper page of the block of multilevel memory cells.

### Claim 12 (depends on 9)

The method of claim 9, further comprising transmitting a confirmation message responsive to storing the first set of write data in the page of the block of single level memory cells.

### Claim 13 (depends on 9)

The method of claim 9, further comprising responsive to detecting the power loss event, determining whether the first set of write data stored in the lower page of the block of multilevel memory cells is corrupted.

### Claim 14 (depends on 9)

The method of claim 9, wherein the first set of write data are stored in the lower page of the block of multilevel memory cells and the second set of write data is stored in the upper page of the block of multilevel memory cells based on a page map.