# US 10,372,359 B2 · Processor for realizing at least two categories of functions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,359 B2 - Document ID: US10372359B2 - Status: Granted - Kind: B2 - Application number: 15/591,205 - Filed: 2017-05-10 - Published: 2017-11-16 - Granted: 2019-08-06 - Earliest claimed: 2016-05-10 - Assignees: ChengDu HaiCun IP Technology LLC; Guobiao Zhang - Applicants: ChengDu HaiCun IP Technology LLC - Inventors: Guobiao Zhang - Web page: https://patentgrep.com/patent/US10372359B2 ## CPC - G06F 3/0629: {Configuration or reconfiguration of storage systems} - G06F 3/0617: {in relation to availability} - G06F 3/0683: {Plurality of storage devices} - G06F 12/00: Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) - G11C 5/005: {Circuit means for protection against loss of information of semiconductor storage devices} - G11C 17/10: in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM - G11C 29/76: {using address translation or modifications} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present invention discloses a first preferred processor comprising a fixed look-up table circuit (LTC) and a writable LTC. The fixed LTC realizes at least a common function while the writable LTC realizes at least a non-common function. The present invention further discloses a second preferred processor comprising a two-dimensional (2-D) LTC and a three-dimensional (3-D) LTC. The 2-D LTC realizes at least a fast function while the 3-D LTC realizes at least a non-fast function. ## Claims ### Claim 1 A processor for realizing at least two categories of functions, comprising: a printed memory array for storing at least a first portion of a first look-up table (LUT) for a first mathematical function, wherein data in said first LUT are physically written into said printed memory array during the manufacturing process of said printed memory array; a writable memory array for storing at least a second portion of a second LUT for a second mathematical function, wherein data in said second LUT can be electrically written into said writable memory array after the manufacturing process of said writable memory array; wherein said printed memory array and said writable memory array comprise physically different memory cells. ### Claim 2 (depends on 1) The processor according to claim 1, wherein said printed memory array is a two-dimensional (2-D) printed memory array. ### Claim 3 (depends on 1) The processor according to claim 1, wherein said printed memory array is a three-dimensional (3-D) printed memory array. ### Claim 4 (depends on 1) The processor according to claim 1, wherein said writable memory array is a 2-D writable memory array. ### Claim 5 (depends on 1) The processor according to claim 1, wherein said writable memory array is a 3-D writable memory array. ### Claim 6 (depends on 1) The processor according to claim 1, wherein data in said first LUT are physically written into said printed memory array using a printing method. ### Claim 7 (depends on 6) The processor according to claim 6, wherein said printing method includes photo-lithography, nano-imprint, e-beam lithography, DUV lithography, and laser programming. ### Claim 8 (depends on 1) The processor according to claim 1, wherein data in said second LUT are electrically written into said writable memory array using an electrical programming method. ### Claim 9 (depends on 1) The processor according to claim 1, wherein said writable memory array is an OTP memory array. ### Claim 10 (depends on 1) The processor according to claim 1, wherein said writable memory array is a re-programmable memory array. ### Claim 11 A processor for realizing at least two categories of functions, comprising: a semiconductor substrate; a two-dimensional (2-D) memory array on said semiconductor substrate for storing at least a third portion of a third look-up table (LUT) for a third mathematical function; a three-dimensional (3-D) memory array above said semiconductor substrate for storing at least a fourth portion of a fourth LUT for a fourth mathematical function; wherein said 2-D memory array and said 3-D memory array are located on different physical levels. ### Claim 12 (depends on 11) The processor according to claim 11, wherein 2-D memory array is a first printed memory array; and, said 3-D memory array is a second printed memory array. ### Claim 13 (depends on 11) The processor according to claim 11, wherein 2-D memory array is a printed memory array; and, said 3-D memory array is a writable memory array. ### Claim 14 (depends on 11) The processor according to claim 11, wherein 2-D memory array is a writable memory array; and, said 3-D memory array is a printed memory array. ### Claim 15 (depends on 11) The processor according to claim 11, wherein 2-D memory array is a first writable memory array; and, said 3-D memory array is a second writable memory array. ### Claim 16 (depends on 11) The processor according to claim 11, wherein said 2-D memory array is faster than said 3-D memory array. ### Claim 17 (depends on 11) The processor according to claim 11, wherein said 3-D memory array has a lower storage cost than said 2-D memory array. ### Claim 18 (depends on 11) The processor according to claim 11, wherein said 3-D memory array at least partially covers said 2-D memory array. ### Claim 19 (depends on 11) The processor according to claim 11, further comprising an arithmetic logic circuit (ALC) on said semiconductor substrate for performing arithmetic operations on selected data from said third or fourth LUT. ### Claim 20 (depends on 19) The processor according to claim 19, wherein said 3-D memory array is stacked above said ALC.