# US 10,372,358 B2 · Access processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,358 B2 - Document ID: US10372358B2 - Status: Granted - Kind: B2 - Application number: 14/941,837 - Filed: 2015-11-16 - Published: 2017-05-18 - Granted: 2019-08-06 - Earliest claimed: 2015-11-16 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Jan Van Lunteren - Web page: https://patentgrep.com/patent/US10372358B2 ## CPC - G06F 3/0629: {Configuration or reconfiguration of storage systems} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0644: {Management of space entities, e.g. partitions, extents, pools} - G06F 3/0673: {Single storage device} - G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)} - G06F 12/0607: {Interleaved addressing} - G06F 2212/1012: Design facilitation - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A reconfigurable computing device having a plurality of reconfigurable partitions and that is adapted to perform parallel processing of operand data by the partitions is provided. The computing system includes a memory device that is adapted to store configuration data to configure the partitions of the computing device, to store operand data to be processed by the configured partitions and to store processing results of the operand data. A programmable memory access processor having a predefined program is provided. The access processor performs address generation, address mapping and access scheduling for retrieving the configuration data from the memory unit, for retrieving the operand data from the memory unit and for storing the processing results in the memory unit. The access processor also transfers the configuration data from the memory unit to the computing device and transfers the operand data from the memory unit to the computing device. ## Claims ### Claim 1 A computing system comprising: at least one reconfigurable computing device, the reconfigurable computing device having a plurality of reconfigurable partitions and being adapted to perform parallel processing of operand data by the partitions; a memory unit adapted to: store configuration data to configure the partitions of the reconfigurable computing device; store operand data to be processed by the configured partitions; and store processing results of the operand data; and a programmable memory access processor comprising a predefined program, the access processor being adapted to: receive a preset configuration time for configuring one or more of the partitions for a processing operation, the preset configuration time is an amount of time that is required for configuring the one or more of the partitions for the processing operation; perform address generation, address mapping and access scheduling for: retrieving the configuration data from the memory unit; retrieving the operand data from the memory unit; and storing the processing results in the memory unit; schedule a transfer time for a transfer of the operand data from the memory unit to the reconfigurable computing device for the processing operation in accordance with the preset configuration time; transfer the configuration data from the memory unit to the reconfigurable computing device; and transfer the operand data from the memory unit to the reconfigurable computing device at the transfer time. ### Claim 2 (depends on 1) A computing system according to claim 1, wherein the reconfigurable computing device is a field programmable gate array (FPGA). ### Claim 3 (depends on 1) A computing system according to claim 1, wherein the memory unit comprises a plurality of memory banks and wherein the access processor is adapted to map the configuration data and/or the operand data over multiple banks. ### Claim 4 (depends on 1) A computing system according to claim 1, wherein the access processor is adapted to control the memory access bandwidth assigned to the retrieval of the configuration data and the operand data according to a predefined scheme. ### Claim 5 (depends on 4) A computing system according to claim 4, wherein the predefined scheme is one of: a round robin scheme and a priority setting scheme. ### Claim 6 (depends on 1) A computing system according to claim 1, wherein the preset configuration time is derived by the access processor from test runs performed to configure the partitions for the processing operation. ### Claim 7 (depends on 6) A computing system according to claim 6, wherein the access processor is adapted to perform a predefined set of configuration operations and/or processing operations according to predefined parameters. ### Claim 8 (depends on 1) A computing system according to claim 1, the computing system comprising a cache memory, the access processor being adapted to store a preselected set of configuration data in the cache memory to facilitate an accelerated configuration of a partition with the preselected configuration data. ### Claim 9 (depends on 1) A computing system according to claim 1, the access processor adapted to: preprocess configuration data stored in the memory unit; and configure a partition of the reconfigurable computing device with the preprocessed configuration data. ### Claim 10 (depends on 1) A computing system according to claim 1, wherein the access processor is adapted to provide a broadcast function, the first broadcast function being provided for transferring the same configuration data simultaneously to multiple partitions. ### Claim 11 (depends on 1) A computing system according to claim 1, wherein the access processor is adapted to: store a map of the configured partitions of the reconfigurable computing device; check, upon receipt of operand data for a processing task, whether a partition is already configured for the processing task; transfer the operand data to the respective partition, if a partition is already configured for the processing task; and configure a new partition for the processing task, if no partition is already configured for the processing task. ### Claim 12 (depends on 1) A computing system according to claim 1, wherein the access processor is adapted to: configure a plurality of partitions for a common processing task; and control the operation of the common processing task in a distributed fashion. ### Claim 13 (depends on 1) A computing system according to claim 1, further comprising at least one host processor, communicatively coupled with the access processor, wherein the access processor is adapted to: receive a configuration data identifier from the host processor, the configuration data identifier indicating a type and identity of the configuration data; and receive an operand data identifier from the host processor, the operand data identifier indicating a processing task to be performed on the operand data. ### Claim 14 (depends on 1) A computing system according to claim 1, wherein the computing system comprises a 3-dimensional chip stack having a plurality of vertical layers, the vertical layers comprising: a plurality of memory layers comprising the memory unit; a logic layer comprising the access processor; and a computing layer comprising the reconfigurable computing device. ### Claim 15 (depends on 14) A computing system according to claim 14, wherein the vertical layers are coupled via Through Silicon Vias (TSVs) and wherein the access processor is adapted to retrieve and transfer the operand data and the configuration data via the TSVs. ### Claim 16 (depends on 14) A computing system according to claim 14, wherein the 3-dimensional chip stack comprises a plurality of vertical columns of memory partitions (vaults), wherein each vault further comprises an access processor in the logic layer and a computing device in the computing layer. ### Claim 17 A computer implemented method for operating a computing system, the computing system comprising at least one reconfigurable computing device with a plurality of reconfigurable partitions, a memory unit and a programmable memory access processor, the method comprising: storing, by the memory unit, configuration data to configure the partitions of the reconfigurable computing device; storing, by the memory unit, operand data to be processed by the configured partitions; storing, by the memory unit, processing results of the operand data; receiving, by the programmable memory access processor, a preset configuration time for configuring one or more of the partitions for a processing operation, the preset configuration time is an amount of time that is required for configuring the one or more of the partitions for the processing operation; performing, by the programmable memory access processor, address generation, address mapping and access scheduling according to a predefined program for: retrieving the configuration data from the memory unit; retrieving the operand data from the memory unit; and storing the processing results in the memory unit; scheduling, by the programmable memory access processor, a transfer time for a transfer of the operand data from the memory unit to the reconfigurable computing device for the processing operation in accordance with the preset configuration time; transferring, by the programmable memory access processor, the configuration data from the memory unit to the reconfigurable computing device; and transferring, by the programmable memory access processor, the operand data from the memory unit to the reconfigurable computing device at the transfer time. ### Claim 18 (depends on 17) A computer implemented method according to claim 17, the method comprising: mapping, by the access processor, the configuration data and/or the operand data over multiple banks of the memory unit. ### Claim 19 (depends on 17) A computer implemented method according to claim 17, the method comprising: controlling, by the access processor, the memory access bandwidth assigned to the configuration data and the operand data according to a predefined scheme. ### Claim 20 A computer program product for operating a programmable memory access processor of a computing system, the computing system comprising at least one reconfigurable computing device with a plurality of reconfigurable partitions, a memory unit and the programmable memory access processor, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by the access processor to cause the access processor to perform a method comprising: receiving a preset configuration time for configuring one or more of the partitions for a processing operation, the preset configuration time is an amount of time that is required for configuring the one or more of the partitions for the processing operation; performing address generation, address mapping and access scheduling according to the program instructions for: retrieving, from the memory unit, configuration data to configure the partitions of the reconfigurable computing device; retrieving, from the memory unit, operand data to be processed by the configured partitions; and storing processing results of the operand data in the memory unit; scheduling a transfer time for a transfer of the operand data from the memory unit to the reconfigurable computing device for the processing operation in accordance with the preset configuration time; transferring the configuration data from the memory unit to the reconfigurable computing device; and transferring the operand data from the memory unit to the reconfigurable computing device at the transfer time.