# US 10,372,197 B2 · User level control of power management policies

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- Number: US 10,372,197 B2
- Document ID: US10372197B2
- Status: Granted
- Kind: B2
- Application number: 15/367,330
- Filed: 2016-12-02
- Published: 2017-03-23
- Granted: 2019-08-06
- Earliest claimed: 2011-12-15
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Krishnakanth V. Sistla; Jeremy Shrall; Stephen H. Gunther; Efraim Rotem; Alon Naveh; Eliezer Weissmann; Anil Aggarwal; Martin T. Rowland; Ankush Varma; Ian M. Steiner; Matthew Bace; Avinash N. Ananthakrishnan; Jason Brandt
- Web page: https://patentgrep.com/patent/US10372197B2

## CPC

- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 1/266: {Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips}
- G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode
- G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality
- G06F 1/3234: Power saving characterised by the action undertaken
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

## Claims

### Claim 1

A processor comprising:
a plurality of cores;
a cache memory;
an interconnect to couple the plurality of cores and the cache memory; and
a power controller to control a plurality of power management features of the processor, wherein the power controller includes a tuning circuit to receive a workload configuration input regarding a workload, receive a plurality of energy performance bias (EPB) values and determine a global EPB value based thereon, and update at least one setting of at least one of the plurality of power management features based on the workload configuration input and the global EPB value.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the power controller is to access a power-performance tuning table based on the workload configuration input and the global EPB value, and use information from the power-performance tuning table to update the at least one setting.

### Claim 3 (depends on 2)

The processor of claim 2, wherein the tuning circuit is to update the at least one setting of the at least one power management feature responsive to the global EPB value.

### Claim 4 (depends on 3)

The processor of claim 3, wherein the tuning circuit includes a sampler to receive the plurality of EPB values from at least some of the plurality of cores and a combiner to generate the global EPB value from the EPB value from the plurality of cores.

### Claim 5 (depends on 4)

The processor of claim 4, wherein the sampler is to receive the EPB value from a plurality of threads to execute on the at least some of the plurality of cores.

### Claim 6 (depends on 4)

The processor of claim 4, wherein the power controller is to generate a bin value from the global EPB value and to access the power-performance tuning table using the bin value.

### Claim 7 (depends on 3)

The processor of claim 3, wherein the tuning circuit is to update at least one setting of a first power management feature controlled by the power controller, and send a message to an interconnect that couples the processor to a second component of a system to update at least one setting of a second power management feature controlled by the interconnect.

### Claim 8 (depends on 2)

The processor of claim 2, wherein the power-performance tuning table includes a plurality of entries each having a plurality of fields each associated with a range of the EPB value and including a setting for a power management feature.

### Claim 9 (depends on 1)

The processor of claim 1, wherein the processor is to receive at least one EPB value from a baseboard management controller.

### Claim 10 (depends on 1)

The processor of claim 1, wherein the at least one EPB value is to be provided based at least in part on a time of day policy.

### Claim 11

A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
receiving an energy performance bias (EPB) value in a tuning circuit of a power control logic of a processor from a plurality of threads executing on the processor and determining a global EPB value based at least in part on the EPB value received from the plurality of threads, the EPB value to indicate a preference of a user for a tradeoff between power optimization and performance optimization;
accessing a table based on the global EPB value; and
updating at least one setting of a power management feature controlled by the power control logic based on information obtained from the table.

### Claim 12 (depends on 11)

The non-transitory machine-readable medium of claim 11, wherein the method further comprises selecting a bin of a plurality of bins, each associated with a power-performance profile using the global EPB value.

### Claim 13 (depends on 11)

The non-transitory machine-readable medium of claim 11, wherein the method further comprises providing an interface to enable a user, an operating system or a baseboard management controller to set the EPB value, and controlling a plurality of power management features via input of the EPB value.

### Claim 14 (depends on 11)

The non-transitory machine-readable medium of claim 11, wherein the method further comprises receiving the EPB value with a first value for a first portion of a day and with a second value for a second portion of the day, wherein the first value is to configure a system for first performance during the first portion of the day corresponding to peak user hours, and the second value to configure the system for higher power savings during the second portion of the day corresponding to non-peak user hours.

### Claim 15

A system comprising:
a multicore processor including a plurality of cores, at least one cache memory and a memory controller;
a tuning circuit to dynamically select a balance between power consumption and performance based on an energy performance bias (EPB) value, wherein the tuning circuit is to access an entry of a tuning table based at least in part on the EPB value and a workload configuration value and update a setting for a power management feature responsive to a value stored in a field of the entry, wherein the workload configuration value is to indicate a predominant workload type to be executed on the system, the tuning table including a first set of entries associated with a first workload type and a second set of entries associated with a second workload type; and
a system memory coupled to the multicore processor via a memory interconnect.

### Claim 16 (depends on 15)

The system of claim 15, wherein the tuning circuit is to update at least one setting of a first power management feature controlled by a power control logic of the multicore processor, the at least one setting obtained from a field of an entry of the tuning table associated with a bin in which the EPB value is included.

### Claim 17 (depends on 16)

The system of claim 16, wherein multicore processor comprises the tuning circuit.

### Claim 18 (depends on 15)

The system of claim 15, wherein the multicore processor comprises a power control logic, the power control logic comprising the tuning circuit, wherein the tuning circuit is to generate a bin value from the EPB value and access the tuning table using the bin value.

### Claim 19 (depends on 1)

The processor of claim 1, wherein the power controller is to enable a first power management feature based on the updated at least one setting.

### Claim 20 (depends on 1)

The processor of claim 1, wherein the power controller is to send an update message to a destination agent of the processor to cause the destination agent to control a first power management feature based on the updated at least one setting.