# US 10,372,180 B2 · Factory reset apparatus and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,372,180 B2 - Document ID: US10372180B2 - Status: Granted - Kind: B2 - Application number: 16/013,954 - Filed: 2018-06-21 - Published: 2018-10-18 - Granted: 2019-08-06 - Earliest claimed: 2015-12-21 - Assignees: Huawei Technologies Co., Ltd. - Applicants: Huawei Technologies Co., Ltd. - Inventors: Ruhong Zhang; Jinbo Ding; Zhengsheng Xie - Web page: https://patentgrep.com/patent/US10372180B2 ## CPC - G06F 1/24: Resetting means - G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C) - H03K 3/356: Bistable circuits - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A factory reset apparatus includes a reset switch, a first power supply module, a flip-flop, and a CPU. The flip-flop includes a data input pin, a clock pin, and a true flip-flop output pin. The reset switch is connected to the data input pin, the first power supply module is connected to the clock pin, and the true flip-flop output pin is connected to the CPU. The reset switch generates a low-level reset signal when being pressed; the flip-flop receives an electrical signal from the clock pin. A rising edge of the electrical signal triggers the flip-flop to latch a low-level state of the reset signal. The flip-flop outputs a low-level reset request signal from the true flip-flop output pin according to the latched low-level state of the reset signal. The CPU starts a factory reset operation according to the reset request signal. ## Claims ### Claim 1 A factory reset apparatus, comprising a reset switch, a first power supply module, a flip-flop, and a processor, wherein the flip-flop comprises a data input pin, a clock pin, and a true flip-flop output pin, wherein the reset switch is connected to the data input pin; the first power supply module is connected to the clock pin; and the true flip-flop output pin is connected to a first general purpose input/output (GPIO) pin of the processor; and, wherein the reset switch is configured to generate a low-level reset signal when being pressed, wherein the low-level reset signal is input into the flip-flop from the data input pin; the flip-flop is configured to receive an electrical signal from the clock pin, wherein a rising edge of the electrical signal triggers the flip-flop to latch a low-level state of the low-level reset signal; the flip-flop is configured to output a low-level reset request signal from the true flip-flop output pin according to the latched low-level state of the low-level reset signal; and the processor is configured to start a factory reset operation according to a reset request signal input from the first GPIO pin. ### Claim 2 (depends on 1) The apparatus according to claim 1, wherein the first power supply module is further connected to a power input pin and a ground pin of the flip-flop; the first power supply module is configured to supply, after being powered on, working power to the flip-flop; and the apparatus further comprises a delay circuit, wherein the first power supply module is connected to the clock pin by using the delay circuit; and an original signal that is output by the first power supply module when being powered on passes through the delay circuit and is output as the electrical signal. ### Claim 3 (depends on 1) The apparatus according to claim 1, further comprising a second power supply module, wherein the second power supply module is connected to a power input pin and a ground pin of the flip-flop, and the second power supply module supplies, after being powered on, working power to the flip-flop; the second power supply module is powered on earlier than the first power supply module; and the first power supply module outputs the electrical signal when being powered on. ### Claim 4 (depends on 1) The apparatus according to claim 1, wherein the flip-flop further comprises a preset pin, and the preset pin is connected to a second GPIO pin of the processor; the processor is further configured to: after starting the factory reset operation according to the low-level reset request signal, output a reset control signal by using the second GPIO pin, wherein the reset control signal is input into the flip-flop from the preset pin; and the flip-flop performs a reset operation according to the reset control signal. ### Claim 5 (depends on 4) The apparatus according to claim 4, wherein the reset control signal is a low-level signal, and a low-level reset control signal is input into the flip-flop from the preset pin, so that the true flip-flop output pin of the flip-flop outputs a high-level signal. ### Claim 6 (depends on 4) The apparatus according to claim 4, wherein the flip-flop is further configured to determine, according to the reset control signal input from the preset pin, that the second GPIO pin is in a high-impedance state, so that a level of the preset pin is pulled up to a power supply level by using a pull-up resistor. ### Claim 7 A factory reset method, wherein the method is applied to a factory reset apparatus, and the factory reset apparatus comprises a reset switch, a first power supply module, a flip-flop, and a processor, wherein the flip-flop comprises a data input pin, a clock pin, and a true flip-flop output pin, wherein the reset switch is connected to the data input pin, the first power supply module is connected to the clock pin, and the true flip-flop output pin is connected to a first general purpose input/output (GPIO) pin of the processor; and, wherein the method comprises: generating, by the reset switch, a low-level reset signal when being pressed, wherein the low-level reset signal is input into the flip-flop from the data input pin; receiving, by the flip-flop, an electrical signal from the clock pin, wherein a rising edge of the electrical signal triggers the flip-flop to latch a low-level state of the low-level reset signal; outputting, by the flip-flop, a low-level reset request signal from the true flip-flop output pin according to the latched low-level state of the low-level reset signal; and starting, by the processor, a factory reset operation according to a reset request signal input from the first GPIO pin. ### Claim 8 (depends on 7) The method according to claim 7, wherein the factory reset apparatus further comprises a delay circuit, the first power supply module is connected to the clock pin by using the delay circuit, and the first power supply module is further connected to a power input pin and a ground pin of the flip-flop; and before the receiving, by the flip-flop, an electrical signal from the clock pin, the method further comprises: supplying, by the first power supply module after being powered on, working power to the flip-flop by using the power input pin and the ground pin of the flip-flop; and outputting, by the first power supply module when being powered on, an original signal to the delay circuit, wherein the original signal passes through the delay circuit and is output as the electrical signal. ### Claim 9 (depends on 7) The method according to claim 7, wherein the factory reset apparatus further comprises a second power supply module, the second power supply module is connected to a power input pin and a ground pin of the flip-flop, and the second power supply module is powered on earlier than the first power supply module; and before the receiving, by the flip-flop, an electrical signal from the clock pin, the method further comprises: supplying, by the second power supply module after being powered on, working power to the flip-flop; and outputting, by the first power supply module, the electrical signal when being powered on. ### Claim 10 (depends on 7) The method according to claim 7, wherein the flip-flop further comprises a preset pin, and the preset pin is connected to a second GPIO pin of the processor; and the method further comprises: after the processor starts the factory reset operation according to the low-level reset request signal, outputting, by the processor, a reset control signal by using the second GPIO pin, wherein the reset control signal is input into the flip-flop from the preset pin; and performing, by the flip-flop, a reset operation according to the reset control signal. ### Claim 11 (depends on 10) The method according to claim 10, further comprising: pulling the preset pin to a high-level state by using a pull-up resistor when the second GPIO pin is in a high-impedance state. ### Claim 12 (depends on 8) The method according to claim 8, wherein the factory reset apparatus further comprises an edge steep circuit, the method further comprises: increasing a steepness of a rising edge of the electrical signal by using the edge steep circuit. ### Claim 13 (depends on 2) The apparatus according to claim 2, further comprising: an edge steep circuit connected to the delay circuit and configured to increase a steepness of a rising edge of the electrical signal. ### Claim 14 (depends on 3) The apparatus according to claim 3, wherein the flip-flop further comprises a clear pin connected to the second power supply module. ### Claim 15 (depends on 4) The apparatus according to claim 4, wherein the flip-flop further comprises a pull-up resistor configured to pull the preset pin to a high-level state when the second GPIO pin is in a high-impedance state.