# US 10,372,002 B2 · Display device

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- Number: US 10,372,002 B2
- Document ID: US10372002B2
- Status: Granted
- Kind: B2
- Application number: 15/647,564
- Filed: 2017-07-12
- Published: 2018-03-01
- Granted: 2019-08-06
- Earliest claimed: 2016-08-30
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Whee-Won Lee; Ga-Na Kim
- Web page: https://patentgrep.com/patent/US10372002B2

## CPC

- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- G02F 1/133: Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements (arrangements or circuits for control of liquid crystal elements in a matrix, not structurally associated with these elements G09G3/36)
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/3208: organic, e.g. using organic light-emitting diodes [OLED]
- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/36: using liquid crystals
- G09G 3/3607: {for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels (display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127)}
- G09G 3/3677: {suitable for active matrices only}
- G09G 3/3611: {Control of matrices with row and column drivers}
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A display device includes: pixels; gate lines for connecting to the pixels; a first gate driving block for connecting to first and second gate lines that are adjacent to each other; and a second gate driving block for connecting to the first gate line and the second gate line, wherein the first gate driving block includes: a first gate signal generating portion; a first transistor connected between a first output terminal of the first gate signal generating portion and the first gate line; and a second transistor connected between the first output terminal and the second gate line, wherein the second gate driving block includes: a second gate signal generating portion; a third transistor connected between a second output terminal of the second gate signal generating portion and the first gate line; and a fourth transistor connected between the second output terminal and the second gate line.

## Claims

### Claim 1

A display device, comprising:
a plurality of pixels;
a plurality of gate lines configured to be connected to the plurality of pixels;
a first gate driver configured to be connected to the plurality of gate lines and include a plurality of first gate driving blocks;
a second gate driver configured to be connected to the plurality of gate lines connected to the first gate driver and include a plurality of second gate driving blocks;
a first gate driving block og the plurality of gate driving blocks configured to be connected to a first gate line and a second gate line of the plurality of gate lines, wherein the first and second gate lines are adjacent to each other; and
a second gate driving block of the plurality of gate driving blocks configured to be connected to the first gate line and the second gate line,
wherein the first gate driving block includes:
a first gate signal generating portion;
a first switching transistor directly connected to a first output terminal of the first gate signal generating portion and the first gate line; and
a second switching transistor directly connected to the first output terminal and the second gate line,
wherein the second gate driving block includes:
a second gate signal generating portion;
a third switching transistor directly connected to a second output terminal of the second gate signal generating portion and the first gate line; and
a fourth switching transistor directly connected to the second output terminal and the second gate line.

### Claim 2 (depends on 1)

The display device of claim 1, wherein the first switching transistor is the same type as that of the fourth switching transistor, and
the second switching transistor is a different type from that of the first switching transistor and is the same type as that of the third switching transistor.

### Claim 3 (depends on 2)

The display device of claim 2, wherein a first switching signal is applied to a gate electrode of each of the first to fourth switching transistors.

### Claim 4 (depends on 3)

The display device of claim 3, wherein a voltage level of the first switching signal is different in consecutive frames.

### Claim 5 (depends on 1)

The display device of claim 1, wherein the first to fourth switching transistors are the same type.

### Claim 6 (depends on 5)

The display device of claim 5, wherein the first switching signal is applied to a gate electrode of each of the first switching transistor and the fourth switching transistor, and
a second switching signal having a voltage level of an opposite phase to that of the first switching signal is applied to a gate electrode of each of the second switching transistor and the third switching transistor.

### Claim 7 (depends on 6)

The display device of claim 6, wherein a voltage level of the first switching signal varies for consecutive frames, and a voltage level of the second switching signal has an opposite phase to that of the first switching signal for the consecutive frames.

### Claim 8 (depends on 1)

The display device of claim 1, wherein the first gate signal generating portion includes:
an output portion configured to output a gate signal to the first output terminal according to a voltage of a first node and a clock signal received by a clock terminal, and
a transmission signal generating portion configured to output a transmission signal to a transmission signal output terminal according to the voltage of the first node and the clock signal, wherein the transmission signal is transmitted to another first gate signal generating portion.

### Claim 9 (depends on 8)

The display device of claim 8, wherein the first gate signal generating portion further includes:
a pull-down driver configured to transmit a first low voltage to the first output terminal and to transmit a second low voltage lower than the first low voltage to the transmission signal output terminal.

### Claim 10 (depends on 9)

The display device of claim 9, wherein the first gate signal generating portion further includes:
a pull-up driver configured to transmit the clock signal to a second node.

### Claim 11 (depends on 10)

The display device of claim 10, wherein the pull-down driver includes a transistor that transmits the second low voltage to the transmission signal output terminal according to a voltage of the second node.

### Claim 12 (depends on 8)

The display device of claim 8, wherein the first gate signal generating portion further includes an input portion that transmits a signal received by an input terminal connected to an output terminal of the another first gate signal generating portion to the first node.