# US 10,371,997 B2 · Array substrate, method of manufacturing the same, and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,371,997 B2 - Document ID: US10371997B2 - Status: Granted - Kind: B2 - Application number: 15/726,995 - Filed: 2017-10-06 - Published: 2018-02-01 - Granted: 2019-08-06 - Earliest claimed: 2014-04-30 - Assignees: Boe Technology Group Co., Ltd.; Beijing Boe Display Technology Co., Ltd. - Applicants: BOE Technology Group Co., Ltd.; Beijing BOE Display Technology Co., Ltd. - Inventors: Xiaowei Liu; Xi Chen; Zhenfei Cai; Yao Liu; Liangliang Li; Zongjie Guo - Web page: https://patentgrep.com/patent/US10371997B2 ## CPC - G02F 1/13458: {Terminal pads} - H10D 86/021: {of multiple TFTs} - H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics} - H10D 86/60: wherein the TFTs are in active matrices - H10W 20/01: {Manufacture or treatment} - G02F 1/13456: {Cell terminals located on one side of the display only} - H10D 86/441: {Interconnections, e.g. scanning lines} - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product. ## Claims ### Claim 1 An array substrate, comprising: a gate line PAD region and a data line PAD region; wherein the gate line PAD region of the array substrate further comprises: gate-line wirings, which are parallel to gate lines and are electrically insulated from the gate lines, are formed between adjacent gate lines, and wherein the data line PAD region of the array substrate further comprises: data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are formed between adjacent data lines, wherein both the gate-line wirings and the data-line wirings are conductive wiring segments; wherein the gate-line wirings are configured to be used as restoring gate lines once the gate lines are scratched, and the data-line wirings are configured to be used as restoring data lines once the data lines are scratched; wherein the gate-line wirings further include first gate-line wiring segments and second gate-line wiring segments being formed between adjacent gate lines, wherein, the first gate-line wiring segments are formed in a same layer as the gate lines are formed, the second gate-line wiring segments are formed above an insulating layer provided on the gate lines; and the first gate-line wiring segments are formed directly under the second gate-line wiring segments and are covered by the insulating layer; and wherein the data-line wirings further include first data-line wiring segments and second data-line wiring segments being formed between adjacent data lines, wherein, the first data-tine wiring segments are formed in a same layer as the data lines are formed, the second data-line wiring segments are formed above the insulating layer provided on the data lines; and the first data-line wiring segments are formed directly under the second data-line wiring segments and are covered by the insulating layer. ### Claim 2 (depends on 1) The array substrate according to claim 1, wherein the array substrate further comprises a common electrode and a pixel electrode in a display region of the array substrate; wherein the pixel electrode is formed above the common electrode, the second gate-line wiring segments and the second data-line wiring segments are formed in a same layer as the pixel electrode is formed and are formed of a same material as the pixel electrode, wherein the first gate-line wiring segments and the first data-line wiring segments are formed in a same layer as the common electrode is formed and are formed of a same material as the common electrode; or wherein the pixel electrode is formed under the common electrode, the second gate-line wiring segments and the second data-line wiring segments are formed in a same layer as the common electrode is formed and are formed of a same material as the common electrode, wherein the first gate-line wiring segments and the first data-line wiring segments are formed in a same layer as the pixel electrode is formed and are formed of same material as the pixel electrode. ### Claim 3 (depends on 1) The array substrate according to claim 1, wherein a spacing between adjacent gate lines is between 20 μm and 30 μm, and a spacing between adjacent data lines is between 10 μm and 20 μm. ### Claim 4 A method of manufacturing an array substrate, comprising the steps of: in a gate line PAD region of the array substrate, forming gate-line wirings between adjacent gate lines, wherein the gate-line wirings are parallel to the adjacent gate lines and are electrically insulated from the adjacent gate lines; and in a data line PAD region of the array substrate, forming data-line wirings between adjacent data lines, wherein the data-line wirings are parallel to the adjacent data lines and are electrically insulated from the adjacent data lines, wherein both the gate-line wirings and the data-line wirings are conductive wiring segments; wherein the gate-line wirings are configured to be used as restoring gate lines once gate lines of adjacent gate lines are scratched, and the data-line wirings are configured to be used as restoring data lines once the data lines of the adjacent data lines are scratched; wherein the step of forming gate-line wirings between adjacent gate lines, wherein the gate-line wirings are parallel to the adjacent gate lines and are electrically insulated from the adjacent gate lines; and the step of forming the data-line wirings between adjacent data lines, wherein the data-line wirings are parallel to the adjacent data lines and are electrically insulated from the adjacent data lines, are performed in parallel and include; depositing a first metal film on a substrate, and forming the data-line wirings spaced apart from each other, in the data line PAD region while forming the adjacent gate lines by a patterning process; depositing an insulating layer on the first metal film and depositing a second metal film on the insulating layer; forming the gate-line wiring provided between the adjacent gate lines in the gate line PAD region while forming the adjacent data lines by a patterning process; wherein the data-line wirings are formed between adjacent data lines, and the gate-line wirings are forming between adjacent gate lines. ### Claim 5 A method of manufacturing an array substrate, comprising the steps of: in a gate line PAD region of the array substrate, forming gate-line wirings between adjacent gate lines, wherein the gate-line wirings are parallel to the adjacent gate lines and are electrically insulated from the adjacent gate lines; and in a data line PAD region of the array substrate, forming data-line wirings between adjacent data lines, wherein the data-line wirings are parallel to the adjacent data lines and are electrically insulated from the adjacent data lines, wherein both the gate-line wirings and the data-line wirings are conductive wiring segments; wherein the gate-line wirings are configured to be used as restoring gate lines once gate lines of adjacent gate lines are scratched, and the data-line wirings are configured to be used as restoring data lines once the data lines of the adjacent data lines are scratched; wherein the step of forming gate-line wirings between adjacent gate lines, wherein the gate-line wirings are parallel to the adjacent gate lines and are electrically insulated from the adjacent gate lines and the step of forming data-line wirings between adjacent data lines, wherein the data-line wirings are parallel to the adjacent data lines and are electrically insulated from the adjacent data lines, are performed in parallel and include: depositing a first transparent conductive film on gate lines and data lines; forming first gate-line wiring segments in the gate line PAD region and first data-line wiring segments in the data line PAD region while forming a pixel electrode in a display region by a patterning process, wherein the first gate-line wiring segments are formed between adjacent gate lines, and the first data-line wiring segments are formed between adjacent data lines; forming an insulating layer and a passivation layer on the array substrate in sequence from bottom to top and depositing a second transparent conductive film on the passivation layer; forming second gate-line wiring segments in the gate line PAD region and second data-line wiring segments in the data line PAD region while forming a common electrode in the display region by a patterning process, wherein the second gate-line wiring segments are formed between adjacent gate lines and the second data-line wiring segments are formed between adjacent data lines; wherein the first gate-line wiring segments are formed directly under the second gate-line wiring segments, and the first data-line wiring segments are formed directly under the second data-line wiring segments. ### Claim 6 A method of manufacturing an array substrate, comprising the steps of: in a gate line PAD region of the array substrate, forming gate-line wirings between adjacent gate lines, wherein the gate-line wirings are parallel to the adjacent gate lines and are electrically insulated from the adjacent gate lines; and in a data line PAD region of the array substrate, forming data-line wirings between adjacent data lines, wherein the data-line wirings are parallel to the adjacent data lines and are electrically insulated from the adjacent data lines, wherein both the gate-line wirings and the data-line wirings are conductive wiring segments; wherein the gate-line wirings are configured to be used as restoring gate lines once gate lines of adjacent gate lines are scratched, and the data-line wirings are configured to be used as restoring data lines once the data lines of the adjacent data lines are scratched; wherein the step of forming gate-line wirings between adjacent gate lines, wherein the gate-line wirings are parallel to the adjacent gate lines and are electrically insulated from the adjacent gate lines; and the step of forming the data-line wirings between adjacent data lines, wherein the data-line wirings are parallel to the adjacent data lines and are electrically insulated from the adjacent data lines, are performed in parallel and include: depositing a first transparent conductive film on gate lines and data lines; forming first gate-line wiring segments in the gate line PAD region and first data-line wiring segments in the data line PAD region while forming a common electrode in a display region by a patterning process, wherein the first gate-line wiring segments are formed between adjacent gate lines, and the first data-line wiring segments are formed between adjacent data lines; forming an insulating layer and a passivation layer on the array substrate in sequence from bottom to top and depositing a second transparent conductive film on the passivation layer; forming second gate-line wiring segments in the gate line PAD region and second data-line wiring segments in the data line PAD region while forming a pixel electrode in the display region by a patterning process, wherein the second gate-line wiring segments are formed between adjacent gate lines and the second data-line wiring segments are formed between adjacent data lines; wherein the first gate-line wiring segments are formed directly under the second gate-line wiring segments, and the first data-line wiring segments are formed directly under the second data-line wiring segments. ### Claim 7 (depends on 1) A display device, including the array substrate according to claim 1. ### Claim 8 (depends on 7) The display device according to claim 7, wherein the array substrate further comprises a common electrode and a pixel electrode, wherein the pixel electrode is formed above the common electrode, the second gate-line wiring segments and the second data-line wiring segments are formed in a same layer as the pixel electrode is formed and are formed by a same material as the pixel electrode, wherein the first gate-line wiring segments and the first data-line wiring segments are formed in a same layer as the common electrode is formed and are formed of a same material as the common electrode; or wherein the pixel electrode is formed under the common electrode, the second gate-line wiring segments and the second data-line wiring segments are formed in a same layer as the common electrode is formed and are formed of a same material as the common electrode, wherein the first gate-line wiring segments and the first data-line wiring segments are formed in a same layer as the pixel electrode is formed and are formed of a same material as the pixel electrode. ### Claim 9 (depends on 7) The display device according to claim 7, wherein a spacing between adjacent gate lines is between 20 μm and 30 μm, and a spacing between adjacent data lines is between 10 μm and 20 μm. ### Claim 10 An array substrate, comprising: a gate line PAD region and a data line PAD region; wherein the gate line PAD region of the array substrate further comprises: gate-line wirings, which are parallel to gate lines and are electrically insulated from the gate lines, are formed between adjacent gate lines, and wherein the data line PAD region of the array substrate further comprises: data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are formed between adjacent data lines, wherein both the gate-line wirings and the data-line wirings are conductive wiring segments; wherein the gate-line wirings are configured to be used as restoring gate lines once the gate lines are scratched, and the data-line wirings are configured to be used as restoring data lines once the data lines are scratched; wherein the gate-line wirings include gate-line wiring segments formed on an insulating layer formed on the gate lines, the gate-line wiring segments are formed between adjacent gate lines; wherein the data-line wirings include data-line wiring segments formed underneath a first portion of the insulating layer formed underneath the data lines, the data-line wiring segments are formed between adjacent data lines; and wherein a second portion of the insulating layer covers the gate-line wiring segments and the data lines, and the gate lines and the data lines are formed in different layers. ### Claim 11 (depends on 10) The array substrate according to claim 10, wherein the gate-line wiring segments are formed in a same layer as the data line are formed and are formed of a same material as the data lines; and wherein the data-line wiring segments are formed in a same layer as the gate lines are formed and are formed of a same material as the gate lines. ### Claim 12 (depends on 10) The array substrate according to claim 10, wherein a spacing between adjacent gate lines is between 20 μm and 30 μm, and a spacing between adjacent data lines is between 10 μm and 20 μm. ### Claim 13 (depends on 10) A display device, including the array substrate according to claim 10. ### Claim 14 (depends on 13) The display device according to claim 13, wherein the gate-line wiring segments are formed in a same layer as the data line are formed and are formed of a same material as the data lines; and wherein the data-line wiring segments are formed in a same layer as the gate lines are formed and are formed of a same material as the gate lines. ### Claim 15 (depends on 13) The display device according to claim 13, wherein a spacing between adjacent gate lines is between 20 μm and 30 μm, and a spacing between adjacent data lines is between 10 μm and 20 μm.