# US 10,371,747 B2 · Physically aware scan diagnostic logic and power saving circuit insertion

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- Number: US 10,371,747 B2
- Document ID: US10371747B2
- Status: Granted
- Kind: B2
- Application number: 15/291,269
- Filed: 2016-10-12
- Published: 2017-09-07
- Granted: 2019-08-06
- Earliest claimed: 2016-03-01
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: William V. Huott; Ankit N. Kagliwal; Mary P. Kusko; Robert C. Redburn
- Web page: https://patentgrep.com/patent/US10371747B2

## CPC

- G01R 31/31721: {Power aspects, e.g. power supplies for test circuits, power saving during test (for scan test G01R31/318575)}
- G01R 31/31704: {Design for test; Design verification (concerning scan tests G01R31/318583; computer-aided design G06F30/00)}
- G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Aspects include a computer-implemented method for scan diagnostic logic circuit insertion in a circuit design topology. A method includes evaluating a scan chain of the circuit design topology, the scan chain comprising a plurality of scan latches and a plurality of physical structures, the evaluating including identifying the plurality of physical structures in the scan chain. The method also includes identifying one of the plurality of physical structures as a physical structure of interest, and responsive to the identification of the physical structure of interest, targeting the physical structure of interest, the targeting comprising inserting scan diagnostic logic at a location in the scan chain that is based on a location of the physical structure of interest in the scan chain.

## Claims

### Claim 1

A computer-implemented method for scan diagnostic logic insertion in a circuit design topology, the method comprising:
evaluating a scan chain of the circuit design topology, the scan chain comprising a plurality of scan latches and a plurality of physical structures, the evaluating including identifying the plurality of physical structures in the scan chain;
identifying one of the plurality of physical structures as a physical structure of interest;
responsive to the identification of the physical structure of interest, targeting the physical structure of interest, the targeting comprising inserting scan diagnostic logic at a location in the scan chain that is based on a location of the physical structure of interest in the scan chain, wherein the inserted scan diagnostic logic is at least one of a multiplexor device, NOR circuit, or XNOR circuit;
disabling a segment of the scan chain associated with the targeted physical structure of interest when the circuit design topology is operating in functional mode to conserve power, wherein the disabling includes providing a scan_disable signal to at least one of the plurality of scan latches;
outputting a signal to a system, wherein the signal is based at least in part on the evaluation; and
propagating results of the evaluating the scan chain to a central processing unit (CPU).

### Claim 2 (depends on 1)

The method of claim 1, wherein the physical structure of interest includes is at least one of a scan path, a long scan net, a metal layer, and a specific latch type.

### Claim 3 (depends on 1)

The method of claim 1, the scan diagnostic logic is inserted at a location in the scan chain that is upstream from the physical structure of interest.

### Claim 4 (depends on 1)

The method of claim 1, further comprising isolating the physical structure of interest, the isolating comprising inserting additional scan diagnostic logic at location in the scan chain that is downstream from the physical structure of interest.

### Claim 5 (depends on 4)

The method of claim 4, wherein the scan diagnostic logic is inserted at a location in the scan chain that is upstream from the physical structure of interest and the location in the scan chain that is downstream from the physical structure of interest is immediately after a downstream scan latch, wherein the downstream scan latch is one of the plurality of scan latches.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
controlling the scan diagnostic logic by applying a global signal to the scan diagnostic logic to prevent switching of the physical structure of interest during functional operation.

### Claim 7 (depends on 1)

The method of claim 1, wherein the physical structure of interest is identified based on a design metric.

### Claim 8 (depends on 1)

The method of claim 1, further comprising, inserting additional scan diagnostic logic at a segment size resolution subsequent to the targeting of the physical structure of interest, wherein the segment size resolution is based on a number of scan latches.

### Claim 9

A computer-implemented method for scan diagnostic logic insertion in a circuit design topology, the method comprising:
evaluating a scan chain of the circuit design topology, the scan chain comprising a plurality of scan latches and a plurality of physical structures, the evaluating including identifying the plurality of physical structures in the scan chain;
identifying one of the plurality of physical structures as a physical structure of interest;
responsive to the identification of the physical structure of interest, targeting the physical structure of interest;
inserting scan diagnostic logic at a location in the scan chain that is based on a location of the physical structure of interest in the scan chain, wherein the inserted scan diagnostic logic is at least one of a multiplexor device, NOR circuit, or XNOR circuit;
disabling a segment of the scan chain associated with the targeted physical structure of interest when the circuit design topology is operating in functional mode to conserve power, wherein the disabling includes providing a scan_disable signal to at least one of the plurality of scan latches;
outputting a signal to a system, wherein the signal is based at least in part on the evaluation; and
propagating results of the evaluating the scan chain to a central processing unit (CPU).