# US 10,369,715 B2 · Semiconductor memory device and method for manufacturing same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,369,715 B2 - Document ID: US10369715B2 - Status: Granted - Kind: B2 - Application number: 15/818,793 - Filed: 2017-11-21 - Published: 2018-03-22 - Granted: 2019-08-06 - Earliest claimed: 2014-06-25 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Toshiyuki Sasaki - Web page: https://patentgrep.com/patent/US10369715B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 16/10: Programming or data input circuits - H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 43/35: with cell select transistors, e.g. NAND - H10D 30/693: {Vertical IGFETs having charge trapping gate insulators} - H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)} - H10P 50/283: {by chemical means} - H10W 20/43: Layouts of interconnections - H10W 20/4441: {the principal metal being a refractory metal} - H10W 20/4446: {Refractory-metal alloys} - A45F 5/021: {to the belt} - B24B 3/54: of hand or table knives - B26B 29/025: {Knife sheaths or scabbards} - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - A45F: TRAVELLING OR CAMP EQUIPMENT: SACKS OR PACKS CARRIED ON THE BODY - B24B: MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING (grinding of gear teeth B23F, of screw-threads B23G1/36; by electro-erosion B23H; abrasive or related blasting B24C; tools for grinding, buffing or sharpening B24D; polishing compositions C09G1/00; abrasives C09K3/14; electrolytic etching or polishing C25F3/00; grinding arrangements for use on assembled railway tracks E01B31/17); DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS - B26B: HAND-HELD CUTTING TOOLS NOT OTHERWISE PROVIDED FOR (for harvesting A01D; for horticulture, for forestry A01G; for butchering or meat treatment A22; for manufactering or repairing footwear A43D; nail clippers or cutters A45D29/02; kitchen equipment A47J; {vegetable slicers, julienne cutters and similar devices and holders therefor, B26D3/28}; for surgical purposes A61B; for metal B23D; cutting by abrasive fluid jets B24C5/02; plier-like tools with cutting edges B25B7/22; pincers B25C11/02; handles for hand implements, in general B25G; guillotine-type cutters B26D; {perforating by non-mechanical means, e.g. by fluid jet, B26F1/26}; for erasing B43L19/00; for textile materials D06H) ## Abstract According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers. ## Claims ### Claim 1 A semiconductor device comprising: first memory cells provided in a first stacked body including a plurality of first electrode layers alternately stacked with a plurality of first insulating layers therebetween, the first memory cells having the first electrode layers as control gates and a first semiconductor portion as channels extending inside the first stacked body; second memory cells provided in a second stacked body including a plurality of second electrode layers alternately stacked with a plurality of second insulating layers therebetween, the second memory cells having the second electrode layers as control gates and a second semiconductor portion as channels extending inside the second stacked body; an interlayer cell having a conductive layer provided above the first stacked body and below the second stacked body and a third semiconductor portion provided between the first semiconductor portion and the second semiconductor portion, the third semiconductor portion having a tubular configuration, and the interlayer cell and the first and second memory cells being connected in series via the first to third semiconductor portions, and an insulating film provided inside the third semiconductor portion having the tubular configuration, wherein the interlayer cell is not used for storing data. ### Claim 2 (depends on 1) The device according to claim 1, wherein the first and second electrode layers include silicon and the first and second insulating layers include silicon oxide. ### Claim 3 (depends on 2) The device according to claim 2, wherein the conductive layer includes silicon. ### Claim 4 (depends on 1) The device according to claim 1, wherein the insulating film includes silicon oxide. ### Claim 5 (depends on 1) The device according to claim 1, wherein the first and second electrode layers and the conductive layer are provided around outer circumferential surfaces of the first to third semiconductor portions. ### Claim 6 (depends on 1) The device according to claim 1, wherein a lower end of a columnar member including the first to third semiconductor portions is connected to a source line and an upper end of the columnar member is connected to a bit line. ### Claim 7 (depends on 1) The device according to claim 1, wherein the first semiconductor portion and the second semiconductor portion have a tubular configuration and the insulating film is further provided inside at least one of the first semiconductor portion and the second semiconductor portion each having the tubular configuration. ### Claim 8 A semiconductor device comprising: first memory cells provided in a first stacked body including a plurality of first electrode layers alternately stacked with a plurality of first insulating layers therebetween, the first memory cells having the first electrode layers as control gates and a first semiconductor portion as channels extending inside the first stacked body; second memory cells provided in a second stacked body including a plurality of second electrode layers alternately stacked with a plurality of second insulating layers therebetween, the second stacked body being stacked above the first stacked body, the second memory cells having the second electrode layers as control gates and a second semiconductor portion as channels extending inside the second stacked body and being electrically connected to the first semiconductor portion; and an intermediate layer provided above the first stacked body and below the second stacked body, the intermediate layer being made of a material different from the first and second electrode layers and the first and second insulating layers, wherein at least one of the first semiconductor portion and the second semiconductor portion has a tubular configuration and a core insulating film is provided inside the tubular configuration of at least one of the first semiconductor portion and the second semiconductor portion. ### Claim 9 (depends on 8) The device according to claim 8, wherein the first and second electrode layers include silicon and the first and second insulating layers include silicon oxide. ### Claim 10 (depends on 8) The device according to claim 8, wherein the material of the intermediate layer includes a metal element. ### Claim 11 (depends on 8) The device according to claim 8, wherein the core insulating film include silicon oxide. ### Claim 12 (depends on 8) The device according to claim 8, wherein the first and second semiconductor portions are included in a columnar member extending in a stacking direction of the first and second stacked bodies, a lower end of the columnar member being connected to a source line and an upper end of the columnar member being connected to a bit line. ### Claim 13 (depends on 12) The device according to claim 12, wherein the columnar member further includes a third semiconductor portion with a tubular configuration between the first semiconductor portion and the second semiconductor portion, the third semiconductor portion extending inside the intermediate layer and being electrically connected to the first and second semiconductor portions, the core insulating film being further provided inside the tubular configuration of the third semiconductor portion. ### Claim 14 (depends on 8) The device according to claim 8, wherein the first and second semiconductor portions are included in a columnar member piercing the first and second stacked bodies and the intermediate layer in a stacking direction of the first and second stacked bodies, and a diameter of the columnar member in a direction perpendicular to the stacking direction is expanded at a height corresponding to the intermediate layer in the stacking direction. ### Claim 15 A semiconductor device comprising: a source layer; first memory cells provided in a first stacked body located above the source layer, the first memory cells including a plurality of first control gate layers alternately stacked with a plurality of first insulating layers therebetween and a first channel body with a tubular configuration extending inside the first stacked body; second memory cells provided in a second stacked body stacked above the first stacked body, the second memory cells including a plurality of second control gate layers alternately stacked with a plurality of second insulating layers therebetween and a second channel body with a tubular configuration extending inside the second stacked body; a bit line provided above the second stacked body, an intermediate layer interposed between the first stacked body and the second stacked body; a first core insulator part provided inside the first channel body with the tubular configuration; and a second core insulator part provided inside the second channel body with the tubular configuration, wherein the first channel body and the second channel body extend in a stacking direction of the first and second stacked bodies and are electrically connected with each other between the source layer and the bit line via a third channel body passing the intermediate layer, the third channel body being bent in the stacking direction inside the intermediate layer, and the first core insulator part has a first central axis extending in the stacking direction and the second core insulator part has a second central axis extending in the stacking direction, an upper end of the first central axis of the first core insulator part being apart from a lower end of the second central axis of the second core insulator part. ### Claim 16 (depends on 15) The device according to claim 15, wherein the intermediate layer is made of a material different from the first and second control gate layers and the first and second insulating layers. ### Claim 17 (depends on 16) The device according to claim 16, wherein the upper end of the first central axis of the first core insulator part is apart from the lower end of the second central axis of the second core insulator part at a height corresponding to the intermediate layer in the stacking direction. ### Claim 18 (depends on 15) The device according to claim 15, wherein the first columnar part and the second columnar part are included in a columnar member piercing the first and second stacked bodies in the stacking direction of the first and second stacked bodies, a lower end of the columnar member being connected to the source layer and an upper end of the columnar member being connected to the bit line. ### Claim 19 (depends on 15) The device according to claim 15, wherein the first and second control gate layers include silicon and the first and second insulating layers include silicon oxide. ### Claim 20 (depends on 15) The device according to claim 15, wherein the first and second core insulator parts include silicon oxide.