Sparse cascaded-integrator-comb filters

A method for operating a cascaded-integrator-comb (CIC) filter with low memory requirements, comprising:

• receiving input values by a last integrating stage of the CIC filter from an output of previous integrating stages;
• sequentially multiplying, at an input of an integrator in the last integrating stage each input value with a corresponding coefficient in a set of coefficients, wherein the set of coefficients are restricted to values between −4 and +4;
• and
• decimating an output of the integrator in the last integrating stage and supplying decimated values to a differentiator of the CIC filter.

A hardware-efficient finite impulse response (FIR) filter embedded in a cascaded-integrator-comb (CIC) filter comprising:

• an input to receive signal values from an integrating stage of the CIC filter;
• and
• a multiplier to implement time-varying input gain based on a set of coefficients selected to sparsely correspond to a desired response of the FIR filter, and sequentially multiply each signal value with a corresponding coefficient of the set of coefficients;
• an integrator to integrate an output from the multiplier;
• and
• a decimator to decimate an output of the integrator;
• wherein the set of coefficients comprises at least one zero, and the multiplier disables the integrator when the corresponding coefficient of the set of coefficients is zero for a given cycle.

A hardware-efficient cascaded-integrator-comb (CIC) filter having an improved frequency response, comprising:

• an integrator;
• time-varying input gain logic, at an input of the integrator, to receive input values from a previous integrator stage in a CIC filter and sequentially apply a corresponding gain coefficient from a set of gain coefficients to each input value, wherein the set of gain coefficients are restricted to values between +4 and −4, and the set of gain coefficients sparsely correspond to a desired finite impulse response filter;
• a decimator to decimate an output of the integrator;
• and
• one or more differentiators in series after the decimator.

A hardware-efficient finite impulse response (FIR) filter embedded in a cascaded-integrator-comb (CIC) filter comprising:

• a first integrator, having a first time-varying input gain logic, to receive an output from a previous integrator stage in the CIC filter, wherein the first time-varying input gain logic applies a first set of coefficients;
• and
• a second integrator, in parallel to the first integrator, having a second time-varying input gain logic, to receive the output from the previous integrator stage in the CIC filter, wherein the second time-varying input gain logic applies a second set of coefficients;
• a first decimator block to decimate an output of the first integrator;
• a second decimator block to decimate an output of the second integrator;
• a delay unit at an output of the first decimator block;
• and
• an adder to combine an output of the delay unit and an output of the second decimator block;
• wherein the first set of coefficients and the second set of coefficients sparsely correspond to a desired response of the FIR filter.

A hardware-efficient apparatus implementing a cascaded-integrator comb (CIC) filter, comprising:

• first multiplying means for sequentially multiplying values from a second to the last integrator by a corresponding coefficient in a first set of coefficients;
• first integrating means for integrating a result from the first multiplying means;
• first decimating means for decimating an output of the first integrating means;
• delaying means for delaying an output of the first integrating means;
• second multiplying means for sequentially multiplying values from a second to the last integrator by a corresponding coefficient in a second set of coefficients;
• second integrating means for integrating a result from the second multiplying means;
• second decimating means for decimating an output of the second integrating means;
• means for combining outputs from the delaying means and the second decimating means and providing the combined outputs to a chain of differentiators;
• and
• wherein the first set of coefficients and the second set of coefficients are constrained to integers between +4 and −4.