US 10,366,835 B2Granted

Plated terminations

AssigneeAVX Corporation

InventorsAndrew P. Ritter, Robert H. Heistand, II, John L. Galvagni, Sriram Dattaguru

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Abstract

Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.

Claims25

Dependent claims

A method of electrically connecting a plurality of interior plates of a multilayer ceramic capacitor having a first surface, a second surface opposite the first surface, and additional exterior surfaces, the plurality of interior plates including each of a plurality of electrode layers and a plurality of anchor tabs, edges of at least some of the plurality of the interior plates being exposed upon at least a portion of the first surface of the ceramic capacitor, and where edges of at least some of the plurality of interior plates are also exposed upon at least a portion of the second surface of the capacitor, the method comprising:

electrolessly plating a first layer of electrically-conductive first metal directly onto the first surface including where the edges of the plurality of interior plates are exposed upon the first surface, the first layer of electrically-conductive first metal on the first surface electrically connecting the edges of the plurality of interior plates that are exposed upon the first surface;
and
concurrently electrolessly plating a first layer of electrically-conductive first metal directly onto the second surface including where the edges of the plates are exposed upon the second surface, the first layer of electrically-conductive first metal on the second surface electrically connecting the edges of the plurality of interior plates that are exposed upon the second surface,
wherein each of the first layer of electrically-conductive first metal on the first surface and the first layer of electrically-conductive first metal on the second surface is not deposited on any of the additional surfaces which meet the first surface, and
wherein the distance between adjacent exposed edges of adjacent plates in a column is not greater than about ten microns.

2 more elements

A method of electrically connecting a plurality of interior plates of a multilayer ceramic capacitor having a first surface, a second surface opposite the first surface, and additional exterior surfaces, the plurality of interior plates including each of a plurality of electrode layers and a plurality of anchor tabs, edges of at least some of the interior plates are exposed upon at least a portion of the first surface of the ceramic capacitor, and where edges of at least some of the interior plates are exposed upon at least a portion of the second surface of the capacitor, the method comprising:

electrolessly plating a first layer of electrically-conductive first metal directly onto the first surface including where edges of the plurality of interior plates are exposed upon the first surface by immersing the entire capacitor in a plating solution, the first layer of electrically-conductive first metal on the first surface electrically connecting the edges of the plurality of interior plates that are exposed upon the first surface;
and
concurrently electrolessly plating a first layer of electrically-conductive first metal directly onto the second surface including where edges of the plurality of interior plates are exposed upon the second surface while the entire capacitor is immersed in the plating solution, the first layer of electrically-conductive first metal on the second surface electrically connecting the edges of the plurality of interior plates that are exposed upon the second surface,
wherein each of the first layer of electrically-conductive first metal on the first surface and the second layer of electrically-conductive first metal on the second surface extends to a third surface and a fourth surface on top of at least two of the plurality of anchor tabs, and
wherein the distance between adjacent exposed edges of adjacent plates in a column is not greater than about ten microns.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/059,984Filed 3 Mar 2016 · continuation
Priority: 15 Apr 2002
Published: US 2016/0189864 A130 Jun 2016
Granted: 30 Jul 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification40 codes

H01G 4/30
Fixed capacitors; Processes of their manufacture: stacked capacitors
C23C 18/1651
Multilayered product: two or more layers only obtained by electroless plating
C23C 18/1653
Multilayered product: two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
C23C 18/32
Coating with metals: coating with nickel, cobalt or mixtures thereof with phosphorus or boron

Family

Application60/372,673Us provisional application · filed 15 Apr 2002
Application10/409,023Parent of this division · filed 8 Apr 2003
Application10/951,972Parent of this continuation · filed 28 Sep 2004
US 7,152,291 B2Parent of this division · filed 26 Dec 2006
US 2016/0189864 A1Pre-grant publication · published 30 Jun 2016
Application10/951,972Parent of this division
US 2003/0231457 A1Published application
US 2005/0046536 A1Published application
US 9,627,132 B2Related patent
US 9,666,366 B2Related patent
US 10,366,835 B2This patent

From the US filing history. Foreign family members aren’t listed.