MTP-Thyristor memory cell circuits and methods of operation
AssigneeSynopsys, Inc.
InventorsColin Stewart Bill, Harry Luan
Life of this patent
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Abstract
An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.
Claims20
A method of verifying a logic state of a selected data memory cell in an array of interconnected memory cells after programming or erasing the selected data memory cell, comprising:
- increasing a word line voltage applied to the selected data memory cell and a reference memory cell associated with the selected data memory cell;
- latching an output of a first sense amplifier at a delayed time after a logic state of an output of a second sense amplifier is switched responsive to increasing the word line voltage, an amount of time between the switching of the logic state of the output of the second sense amplifier and the delayed time representing separation between a threshold voltage of the reference memory cell and a threshold voltage of the selected data memory cell, wherein:
- when verifying programming of the selected data memory cell, the output of the first sense amplifier is an amplified version of an output of the selected data memory cell, and the output of the second sense amplifier is an amplified version of an output of the reference memory cell, and
- when verifying erasing of the selected memory cell, the output of the first sense amplifier is an amplified version of the output of the reference memory cell, and the output of the second sense amplifier is an amplified version of the output of the selected data memory cell;
- and
- determining whether the selected data memory cell has been programmed, or has been erased based on a value of the latched output of the first sense amplifier.
A memory cell reading circuitry for reading a selected memory cell selected from an array of interconnected memory cells, comprising:
- a ramp generation block configured to increase a word line voltage applied to the selected memory cell and a reference memory cell corresponding to the selected memory cell, the word line voltage starting at an initial voltage;
- a first differential sense amplifier configured to receive an output of the selected memory cell, and generate an amplified version of the output of the selected memory cell;
- a circuit configured to generate a signal responsive to an output of the reference memory cell reaching a first predetermined voltage level, the circuit comprising a pulse generation circuit configured to generate a pulse signal responsive to an output of the reference memory cell reaching the first predetermined voltage level, the word line voltage returning to the initial voltage at an end of the pulse signal;
- and
- a latch circuit configured to latch the amplified version of the output of the selected memory cell responsive to receiving the signal generated by the circuit, the latched amplified version of the output of the selected memory cell representing a logic state of the selected data memory cell.
Dependencies are inferred from the claim text.