Back to results
US 10,361,996 B2Granted
Serial bus auto-addressing
AssigneeElmos Semiconductor AG
InventorsChristian Schmitz, Bernd Burchard
Life of this patent
Estimating the term…
Abstract
A bus node is capable of performing a method for the assigning of bus node addresses to bus nodes of a serial data bus. The method is performed with the aid of bus shunt resistors in the individual bus nodes of the data bus system in an assignment time period. After the assigning of bus node addresses to the bus nodes in the assignment time period, there follows an operating time period. For this purpose, the bus node comprises such a bus shunt resistor. The bus node is characterized by a bus shunt bypass switch which, prior to assigning a bus node address to the bus node in the assignment time period is opened and which after the assignment of bus node address to the bus node in the assignment time period is closed, and which is closed in the operating time period.
Claims9
A method for feeding address currents into a bus line via a plurality of bus nodes of a serial data bus system comprising:
- the bus line;
- and
- a bus master connected on a downstream end of the bus line, wherein the plurality of bus nodes are serially connected to the bus line, upstream from the bus master;
- wherein the plurality of bus nodes includes:
- a first bus node, connected to the bus line at a site upstream from, and closest to the bus master;
- a last bus node, connected to the bus line at a site upstream from, and farthest from the bus master;
- and
- zero or more middle bus nodes, connected to the bus line in between the first bus node and the last bus;
- wherein:
- the plurality of bus nodes includes at least two addressable bus nodes to which a respective address is assigned by the bus master in an addressing phase;
- and
- the plurality of bus nodes includes zero or more standard bus nodes having a respective address that is fixed prior to performing the addressing phase;
- the plurality of bus nodes includes zero or more bus nodes operative to feed a respective quiescent current into the bus line;
- wherein, in the method:
- at a beginning of the addressing phase, each of the at least two addressable bus nodes is not-yet-addressed;
- each of the not-yet-addressed addressable bus nodes is operative to feed a respective address current into the bus line;
- each of the not-yet-addressed addressable bus nodes is operative to detect, with aid of a respective current measurement circuit, a respective bus current flowing through the respective not-yet-addressed addressable bus node as a sum of (1) the quiescent currents of bus nodes arranged upstream from the respective not-yet-addressed addressable bus node, (2) the respective address current of the respective not-yet-addressed addressable bus node, and (3) the respective address currents of each of the not-yet-addressed addressable bus nodes arranged upstream from the respective not-yet-addressed addressable bus node;
- during the addressing phase, by analysis of the respective address currents of each of the not-yet-addressed addressable bus nodes, individual bus nodes from the not-yet-addressed addressable bus nodes are identified;
- the method comprising:
- feeding, in one of the not-yet-addressed addressable bus nodes, one of an address current and a test current into a first electrical node of two electrical nodes coupled to the bus line;
- measuring, by a current measurement circuit in the one of the not-yet-addressed addressable bus nodes, a bus current through the one of the not-yet-addressed addressable bus node;
- determining whether the current measurement circuit in the one of the not-yet-addressed addressable bus nodes detects the one of the address current and the test current in the bus current;
- configuring, in a first case that the current measurement circuit in the one of the not-yet-addressed addressable bus nodes detects the one of the address current and the test current in the bus current, the one of the not-yet-addressed addressable bus nodes to feed the address current into the first electrical node of the two electrical nodes coupled to the bus line;
- and
- configuring, in a second case that the current measurement circuit in the one of the not-yet-addressed addressable bus nodes does not detect the one of the address current and the test current in the bus current, the one of the not-yet-addressed addressable bus nodes to feed the address current into a second electrical node of the two electrical nodes coupled to the bus line.
22 more elements
An addressable bus node for a serial data bus system, the data bus system comprising:
- a bus line;
- a bus master connected to a downstream end of the bus line;
- and
- a plurality of bus nodes serially connected to the bus line, the plurality of bus nodes including two or more addressable bus nodes adapted to their respective addresses assigned by the bus master and zero or more standard bus nodes with already fixed addresses, the addressable bus node comprising:
- a current measurement circuit;
- a first addressing current source for feeding an address current into the bus line and via the bus line to the bus master while the address current is detected by the current measurement circuit;
- a quiescent current source for feeding a quiescent current into the bus line and via the bus line to the bus master, wherein the quiescent current source can be identical with the first addressing current source;
- and
- a control unit for controlling at least the first addressing current source for feeding the address current via selectively one of two electrical nodes into the bus line, the two electrical nodes including a first electrical node and a second electrical node;
- wherein:
- the current measurement circuit is arranged between the two first electrical node and the second electrical node;
- the control unit comprises an evaluating unit for detecting one of the first electrical node or the second electrical node at which, upon feeding the address current or a test current, the current measurement circuit detects the address current or the test current, and
- the control unit is configured to configure the addressable bus node such that the address current or the test current is fed into the bus line via the one of the first electrical node or second electrical node at which the current measurement circuit detects the address current or the test current.
10 more elements
A method for feeding address currents into a bus line via a plurality of bus nodes of a serial data bus system comprising:
- the bus line;
- and
- a bus master connected on a downstream end of the bus line, wherein, the plurality of bus nodes are serially connected to the bus line, upstream from the bus master;
- wherein the plurality of bus nodes includes:
- a first bus node, connected to the bus line at a site upstream from, and closest to the bus master;
- a last bus node, connected to the bus line at a site upstream from, and farthest from the bus master;
- and
- zero or more middle bus nodes, connected to the bus line in between the first bus node and the last bus node;
- wherein:
- the plurality of bus nodes includes at least two addressable bus nodes to which a respective address is assigned by the bus master in the addressing phase;
- and
- the plurality of bus nodes includes zero or more standard bus nodes having a respective address that is fixed prior to performing the addressing phase;
- the plurality of bus nodes includes zero or more bus nodes operative to feed a respective quiescent current into the bus line;
- wherein, in said method:
- at a beginning of the addressing phase, each of the at least two addressable bus nodes is not-yet-addressed;
- each of the not-yet-addressed addressable bus nodes is operative to feed a respective address current into the bus line;
- each of the not-yet-addressed addressable bus nodes is operative to detect, with aid of a respective current measurement circuit, a respective bus current flowing through the respective not-yet-addressed addressable bus node as a sum of (1) the quiescent currents of bus nodes arranged upstream from the respective not-yet-addressed addressable bus node, (2) its own address current, and (3) the respective address currents of each of the not-yet-addressed addressable bus nodes arranged upstream from the respective not-yet-addressed addressable bus node;
- during the addressing phase, by analysis of the respective address currents of each of the not-yet-addressed addressable bus nodes, individual bus nodes from the not-yet-addressed addressable bus nodes are identified;
- one of the not-yet-addressed addressable bus nodes is operative to feed a respective address current or a respective test current into the bus line selectively at one of a first electrical node and a second electrical node coupled to the bus line, wherein the current measurement circuit of the not-yet-addressed addressable bus node is arranged between the first electrical node and the second electrical node, and
- the one of the first electrical node and second electrical node is selected for the feeding of the address current at which the current measurement circuit is operative to detect one of the respective address current and the respective test current which is selectively fed into one of the first electrical node and the second electrical node or successively into each of the first electrical node and second electrical node.
17 more elements
Dependencies are inferred from the claim text.