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US 10,360,168 B1Granted
Computing in parallel processing environments
AssigneeMellanox Technologies, Ltd.
InventorsPatrick Robert Griffin, Carl G. Ramey
Life of this patent
Estimating the term…
Abstract
A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.
Claims23
A method executed by a multicore processor device of a computing system, the method comprising:
- dynamically configuring by a mapping engine running on the multicore processor device, a set of mapping regions into a bus interface address space, with the mapping engine maintaining a state comprising an enable bit, a start address, an end address and an operation selector per mapping region;
- decoding an incoming bus request by the mapping engine;
- comparing a target address of the decoded bus request to start and end addresses of each mapped region to determine whether the target address falls within an address range of one of the mapped regions;
- assigning by the mapping engine different operations to different ranges of bus address space;
- and
- determining whether the enable bit is at a first state, and when at the first state, executing an operation selector to determine an operation to perform that will satisfy the bus request.
3 more elements
A multicore processor device comprises:
- a plurality of cores, with multiple ones of the plurality of cores each comprising
- a processor;
- and
- switching circuitry configured to couple the processor to a network among the plurality of cores;
- the multicore processor device further comprising:
- a bus interface;
- and with the multicore processor device comprising:
- a mapping engine that dynamically configures a set of mapping regions, with the mapping engine maintaining a state that comprises an enable bit, a start address, an end address and an operation selector per mapping region to map into a bus interface address space associated with the bus interface;
- decodes an incoming bus request;
- compares a target address of the decoded bus request to start and end addresses of each mapped region to determine whether the target address falls within an address range of one of the mapped regions;
- assigns different operations to different ranges of the bus address space;
- and
- determines whether the enable bit is at a given state, and when at the given state, executes an operation selector to determine an operation to perform that will satisfy the bus request.
10 more elements
Dependencies are inferred from the claim text.