Phase controller apparatus and methods
AssigneeCypress Semiconductor Corporation
InventorsTakuya Kurishita, Yukisato Miyazaki
Life of this patent
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Abstract
A phase controller includes a plurality of pulse width modulation (PWM) circuits, a plurality of switching devices, a computing unit, and a latency generator. The plurality of PWM circuits output pulse signals. The plurality of switching devices are coupled to the respective plurality of PWM circuits, and switch on and off based on the pulse signals. The computing unit calculates the pulse signals to be output from the plurality of PWM circuits, based on outputs of the plurality of switching devices. The latency generator generates latency in any of the pulse signals so that edge positions of the pulse signals output from the plurality of PWM circuits do not collide with each other, wherein the pulse signals change values at the edge positions.
Claims19
A method comprising:
- generating a first set of data values indicative of a changing state of a first pulse signal;
- generating a second set of data values indicating positions of changing state of a second pulse signal;
- determining whether an edge collision occurs by comparing the first and second sets of data values;
- if an edge collision occurs, performing a bit shift on at least the first set of data values;
- and
- generating a target latency set value for at least the first pulse signal based on the bit-shifted first set of data values.
A method comprising:
- evaluating a first pulse signal and a second pulse signal, the evaluating to detect an edge collision between the first and second pulse signals;
- if an edge collision between the first and second pulse signals is detected, shifting the second pulse signal;
- if an edge collision between the first and second pulse signals is not detected:
- evaluating the first pulse signal and a third pulse signal, the evaluating to detect an edge collision between the first and third pulse signals, and
- evaluating the second pulse signal and the third pulse signal, the evaluating to detect an edge collision between the second and third pulse signals,
- if an edge collision between either the first and third pulse signals or the second and third pulse signals is detected, shifting the third pulse signal by one bit, and if the third pulse signal is shifted for one period, shifting the second pulse signal by one bit;
- if an edge collision between either the first and third pulse signals or the second and third pulse signals is not detected, determining that no edge collision is present.
A method comprising:
- calculating a duty ratio of each of a plurality of pulse signals, the plurality of pulse signals output from a plurality of pulse width modulation (PWM) circuits;
- calculating a latency for at least one pulse signal of the plurality of pulse signal;
- and
- providing a latency set value to the at least one pulse signal, the latency set value configured to avoid edge collisions of the plurality of pulse signals,
- wherein the latency set value is derived from a comparison of a set of data values indicative of edge conditions for each of the plurality of pulse signals.
Dependencies are inferred from the claim text.