Systems and methods to visually align signals using delay

A computer implemented method for visualizing signals, comprising:

• receiving and storing, by at least one processor executing an input module, signal samples of a first signal;
• selecting, and storing into a first packet, by the at least one processor executing a packetizer module, a portion of the signal samples of the first signal for a first time period, wherein the first packet comprises a first tag corresponding to the first time period;
• selecting, and storing into a second packet, by the at least one processor executing the packetizer module, a portion of signal samples of the second signal for the first time period, wherein the second packet comprises a second tag corresponding to the first time period;
• processing, by the at least one processor executing a first digital signal processor (DSP) of a first signal module, the first packet associated with the first signal, wherein the processing of the first packet incurs a first processing delay;
• processing, by the at least one processor executing a second DSP of a second signal module, the second packet associated with the second signal, wherein the processing of the second packet incurs a second processing delay;
• equalizing, by the at least one processor executing a configuration path module, the first processing delay of the first DSP with the second processing delay of the second DSP,
• wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet;
• and
• displaying, by the at least one processor executing a display module coupled to the first signal module and the second signal module, the processed first packet and the processed second packet, wherein the processed first packet is displayed approximately simultaneously with the processed second packet being displayed.

A non-transitory computer-readable device having instructions stored thereon that, when executed by at least one computing device, cause the at least one computing device to perform operations comprising:

• receiving and storing, by an input module, signal samples of a first signal;
• selecting, and storing into a first packet, by a packetizer module, the signal samples of the first signal for a first time period, wherein the first packet comprises a first tag corresponding to the first time period;
• selecting, and storing into a second packet, by the packetizer module, a portion of signal samples of a second signal for the first time period, wherein the second packet comprises a second tag corresponding to the first time period;
• processing, by a first digital signal processor (DSP) of a first signal module, the first packet associated with the first signal, wherein the processing of the first packet incurs a first processing delay;
• processing, by a second DSP of a second signal module, the second packet associated with the second signal, wherein the processing of the second packet incurs a second processing delay;
• equalizing, by a configuration path module, the first processing delay of the first DSP with the second processing delay of the second DSP, wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet;
• and
• displaying, by a display module coupled to the first signal module and the second signal module, the processed first packet and the processed second packet, wherein the processed first packet is displayed approximately simultaneously with the processed second packet being displayed.

A system for visualization of signals, comprising:

• a memory comprising:
• a queuing module configured to:
• store a first packet in a first queue associated with a first signal, wherein the first queue enables the first packet to be processed independently;
• and
• store a second packet in a second queue associated with a second signal, wherein the second queue enables the second packet to be processed independently;
• a first signal module comprising a first digital signal processor (DSP) configured to process the first packet associated with the first signal, wherein the processing of the first packet incurs a first processing delay;
• a second signal module comprising a second DSP configured to process the second packet associated with the second signal, wherein the processing of the second packet incurs a second processing delay;
• a packet dispatcher module configured to:
• dispatch the first packet from the first queue to the first signal module based on a global signals table;
• and
• dispatch the second packet from the second queue to the second signal module based on the global signals table;
• a configuration path module configured to equalize the first processing delay of the first DSP with the second processing delay of the second DSP, wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet;
• and
• a display module coupled to the first signal module and the second signal module and configured to display the processed first packet and the processed second packet, wherein the display module is configured to display the processed first packet approximately simultaneously with the processed second packet;
• and
• at least one processor coupled to the memory and configured to execute the queuing module, the first signal module, the second signal module, the packet dispatcher module, the configuration path module, and the display module.

A system for visualization of signals, comprising:

• a memory comprising:
• a first signal module comprising a first digital signal processor (DSP) configured to process a first packet associated with a first signal based on a first tag that corresponds to a first time period, wherein the processing of the first packet incurs a first processing delay;
• a second signal module comprising a second DSP configured to process a second packet associated with a second signal based on a second tag that corresponds to the first time period, wherein the processing of the second packet incurs a second processing delay, and wherein signal samples in the first packet are time aligned with signal samples in the second packet;
• a configuration path module configured to equalize the first processing delay of the first DSP with the second processing delay of the second DSP, wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet;
• and
• a display module coupled to the first signal module and the second signal module and configured to display the processed first packet and the processed second packet, wherein the display module is configured to display the processed first packet approximately simultaneously with the processed second packet;
• and
• at least one processor coupled to the memory and configured to execute the first signal module, the second signal module, the configuration path module, and the display module.

A computer implemented method for visualizing signals:

• storing, by at least one processor executing a queueing module, a first packet in a first queue associated with a first signal, wherein the first queue enables the first packet to be processed independently;
• storing, by the at least one processor executing the queueing module, a second packet in a second queue associated with a second signal, wherein the second queue enables the second packet to be processed independently;
• processing, by the at least one processor executing a first digital signal processor (DSP) of a first signal module, the first packet associated with the first signal, wherein the processing of the first packet incurs a first processing delay;
• processing, by the at least one processor executing a second DSP of a second signal module, the second packet associated with the second signal, wherein the processing of the second packet incurs a second processing delay;
• dispatching, by the at least one processor executing a packet dispatcher module, the first packet from the first queue to the first signal module based on a global signals table;
• dispatching, by the at least one processor executing the packet dispatcher module, the second packet from the second queue to the second signal module based on the global signals table;
• equalizing, by the at least one processor executing a configuration path module, the first processing delay of the first DSP with the second processing delay of the second DSP, wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet;
• and
• displaying, by the at least one processor executing a display module coupled to the first signal module and the second signal module, the processed first packet and the processed second packet, wherein the processed first packet is displayed approximately simultaneously with the processed second packet.

A computer implemented method for visualizing signals:

• processing, by at least one processor executing a first digital signal processor (DSP) of a first signal module, a first packet associated with a first signal based on a first tag that corresponds to a first time period, wherein the processing of the first packet incurs a first processing delay;
• processing, by the at least one processor executing a second DSP of a second signal module, a second packet associated with a second signal based on a second tag that corresponds to the first time period, wherein the processing of the second packet incurs a second processing delay, and wherein signal samples in the first packet are time aligned with signal samples in the second packet;
• equalizing, by the at least one processor executing a configuration path module, the first processing delay of the first DSP with the second processing delay of the second DSP, wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet;
• and
• displaying, by the at least one processor executing a display module coupled to the first signal module and the second signal module, the processed first packet and the processed second packet, wherein the processed first packet is displayed approximately simultaneously with the processed second packet.

A non-transitory computer-readable device having instructions stored thereon that, when executed by at least one computing device, cause the at least one computing device to perform operations comprising:

• storing, by a queueing module, a first packet in a first queue associated with a first signal, wherein the first queue enables the first packet to be processed independently;
• storing, by the queueing module, a second packet in a second queue associated with a second signal, wherein the second queue enables the second packet to be processed independently;
• processing, by a first digital signal processor (DSP) of a first signal module, the first packet associated with the first signal, wherein the processing of the first packet incurs a first processing delay;
• processing, by a second DSP of a second signal module, the second packet associated with the second signal, wherein the processing of the second packet incurs a second processing delay;
• dispatching, by a packet dispatcher module, the first packet from the first queue to the first signal module based on a global signals table;
• dispatching, by the packet dispatcher module, the second packet from the second queue to the second signal module based on the global signals table;
• equalizing, by a configuration path module, the first processing delay of the first DSP with the second processing delay of the second DSP, wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet;
• and
• displaying, by a display module coupled to the first signal module and the second signal module, the processed first packet and the processed second packet, wherein the processed first packet is displayed approximately simultaneously with the processed second packet.

A non-transitory computer-readable device having instructions stored thereon that, when executed by at least one computing device, cause the at least one computing device to perform operations comprising:

• processing, by a first digital signal processor (DSP) of a first signal module, a first packet associated with a first signal based on a first tag that corresponds to a first time period, wherein the processing of the first packet incurs a first processing delay;
• processing, by a second DSP of a second signal module, a second packet associated with a second signal based on a second tag that corresponds to the first time period, wherein the processing of the second packet incurs a second processing delay, and wherein signal samples in the first packet are time aligned with signal samples in the second packet;
• equalizing, by a configuration path module, the first processing delay of the first DSP with the second processing delay of the second DSP, wherein the equalizing causes the first DSP to complete processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet;
• and
• displaying, by a display module coupled to the first signal module and the second signal module, the processed first packet and the processed second packet, wherein the processed first packet is displayed approximately simultaneously with the processed second packet.