Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same

A chip assembly structure comprising:

• a first semiconductor chip comprising a first semiconductor substrate, first semiconductor devices located over a front side surface of the first semiconductor substrate, first through-substrate via structures vertically extending from the front side surface of the first semiconductor substrate to a backside surface of the first semiconductor substrate and are electrically isolated from the first semiconductor substrate by a respective tubular insulating spacer and by a backside insulating layer contacting the backside surface of the first semiconductor substrate, and first backside bonding pad structures located on the first through-substrate via structures at a backside of the first semiconductor substrate, wherein the first semiconductor devices comprise a three-dimensional memory device including an alternating stack of insulating layers and electrically conductive layers and a two-dimensional array of memory stack structures including a respective vertical stack of memory elements located at levels of the electrically conductive layers;
• a second semiconductor chip comprising a second semiconductor substrate, second semiconductor devices located over a front side surface of the second semiconductor substrate, and second bonding pad structures electrically connected to a respective one of the second semiconductor devices, wherein the first backside bonding pad structures are directly bonded to a respective one of the second bonding pad structures, wherein the second semiconductor devices in the second semiconductor chip comprise peripheral devices that provide control signals for operation of the two-dimensional array of memory stack structures in the first semiconductor chip;
• and
• a third semiconductor chip comprising a third semiconductor substrate, third semiconductor devices located over a front side surface of the third semiconductor substrate, and third-chip backside bonding pad structures electrically connected to a respective one of the third semiconductor devices, wherein the first semiconductor chip further comprises first front side bonding pad structures electrically connected to the first backside bonding pad structures and directly bonded to a respective one of the third-chip backside bonding pad structures;
• wherein a subset of the first front side bonding pad structures is electrically shorted to a respective one of the first backside bonding pad structures by a respective one of the first through-substrate via structures and a respective set of metal interconnect structures.

A chip assembly structure comprising:

• a first semiconductor chip comprising a first semiconductor substrate, first semiconductor devices located over a front side surface of the first semiconductor substrate, first through-substrate via structures vertically extending from the front side surface of the first semiconductor substrate to a backside surface of the first semiconductor substrate and are electrically isolated from the first semiconductor substrate by a respective tubular insulating spacer and by a backside insulating layer contacting the backside surface of the first semiconductor substrate, and first backside bonding pad structures located on the first through-substrate via structures at a backside of the first semiconductor substrate, wherein the first semiconductor devices comprise a three-dimensional memory device including an alternating stack of insulating layers and electrically conductive layers and a two-dimensional array of memory stack structures including a respective vertical stack of memory elements located at levels of the electrically conductive layers;
• a second semiconductor chip comprising a second semiconductor substrate, second semiconductor devices located over a front side surface of the second semiconductor substrate, and second bonding pad structures electrically connected to a respective one of the second semiconductor devices, wherein the first backside bonding pad structures are directly bonded to a respective one of the second bonding pad structures, wherein the second semiconductor devices in the second semiconductor chip comprise peripheral devices that provide control signals for operation of the two-dimensional array of memory stack structures in the first semiconductor chip;
• and
• a third semiconductor chip comprising a third semiconductor substrate, third semiconductor devices located over a front side surface of the third semiconductor substrate, and third-chip backside bonding pad structures electrically connected to a respective one of the third semiconductor devices, wherein the first semiconductor chip further comprises first front side bonding pad structures electrically connected to the first backside bonding pad structures and directly bonded to a respective one of the third-chip backside bonding pad structures;
• wherein:
• the first semiconductor chip further comprises sets of metal interconnect structures located between the first semiconductor substrate and the front side bonding pad structures, wherein each set of metal interconnect structures provide an electrically conductive path between a respective pair of a front side bonding pad structure and a first bonding pad structure, and at least one set of metal interconnect structures extends through the alternating stack of insulating layers and electrically conductive layers;
• the first through-substrate via structures and the first backside bonding pad structures are portions of first integrated through-substrate via and pad structures;
• each of the first through-substrate via structures has a greater lateral dimension within a horizontal plane including the front side surface of the first semiconductor substrate than within a horizontal plane including the backside surface of the first semiconductor substrate;
• and
• the tubular insulating spacers comprise thermal silicon oxide that is substantially free of carbon and hydrogen, and the backside insulating layer comprises chemical vapor deposition silicon oxide that includes carbon and hydrogen at atomic concentrations greater than 1 part per million.

A method of forming a chip assembly structure comprising:

• providing a first semiconductor chip comprising a first semiconductor substrate, first semiconductor devices located over a front side surface of the first semiconductor substrate, first through-substrate via structures vertically extending from the front side surface of the first semiconductor substrate to a backside surface of the first semiconductor substrate and are electrically isolated from the first semiconductor substrate by a respective tubular insulating spacer and by a backside insulating layer contacting the backside surface of the first semiconductor substrate, first backside bonding pad structures located on the first through-substrate via structures at a backside of the first semiconductor substrate, and first front side bonding pad structures electrically connected to the first integrated through-substrate via and pad structures, wherein the first semiconductor devices comprise a three-dimensional memory device including an alternating stack of insulating layers and electrically conductive layers and a two-dimensional array of memory stack structures including a respective vertical stack of memory elements located at levels of the electrically conductive layers;
• providing a second semiconductor chip comprising a second semiconductor substrate, second semiconductor devices located over a front side surface of the second semiconductor substrate, and second bonding pad structures electrically connected to a respective one of the second semiconductor devices, wherein the second semiconductor devices in the second semiconductor chip comprise peripheral devices that provide control signals for operation of the three-dimensional memory device of the first semiconductor chip;
• bonding the first backside bonding pad structures to a respective one of the second bonding pad structures by surface activated bonding;
• providing a third semiconductor chip comprising a third semiconductor substrate, third semiconductor devices located over a front side surface of the third semiconductor substrate, and third-chip bonding pad structures electrically connected to a respective one of the third semiconductor devices;
• bonding the first front side bonding pad structures on the first semiconductor chip to a respective one of the third-chip bonding pad structures by surface activated bonding;
• disposing the first backside bonding pad structures directly on the respective one of the second bonding pad structures;
• and
• bonding the first backside bonding pad structures to the second bonding pad structures by copper direct bonding during an anneal process.

A chip assembly structure comprising:

• a first semiconductor chip comprising a first semiconductor substrate, first semiconductor devices located over a front side surface of the first semiconductor substrate, first through-substrate via structures vertically extending from the front side surface of the first semiconductor substrate to a backside surface of the first semiconductor substrate and are electrically isolated from the first semiconductor substrate by a respective tubular insulating spacer and by a backside insulating layer contacting the backside surface of the first semiconductor substrate, and first backside bonding pad structures located on the first through-substrate via structures at a backside of the first semiconductor substrate, wherein the first semiconductor devices comprise a three-dimensional memory device including an alternating stack of insulating layers and electrically conductive layers and a two-dimensional array of memory stack structures including a respective vertical stack of memory elements located at levels of the electrically conductive layers;
• a second semiconductor chip comprising a second semiconductor substrate, second semiconductor devices located over a front side surface of the second semiconductor substrate, and second bonding pad structures electrically connected to a respective one of the second semiconductor devices, wherein the first backside bonding pad structures are directly bonded to a respective one of the second bonding pad structures, wherein the second semiconductor devices in the second semiconductor chip comprise peripheral devices that provide control signals for operation of the two-dimensional array of memory stack structures in the first semiconductor chip;
• a third semiconductor chip comprising a third semiconductor substrate, third semiconductor devices located over a front side surface of the third semiconductor substrate, and third-chip backside bonding pad structures electrically connected to a respective one of the third semiconductor devices, wherein the first semiconductor chip further comprises first front side bonding pad structures electrically connected to the first backside bonding pad structures and directly bonded to a respective one of the third-chip backside bonding pad structures;
• an interposer bonded to a topmost semiconductor chip by solder ball bonding to first bonding pads located on a top surface of the topmost semiconductor chip, wherein the topmost semiconductor chip is selected from the third semiconductor chip or a topmost one of at least one additional semiconductor chip bonded to the third semiconductor chip by copper-to-copper bonding;
• and
• a packaging substrate attached to the interposer, wherein bonding pads of the packaging substrate are electrically connected to second bonding pads of the interposer.

A method of forming a chip assembly structure comprising:

• providing a first semiconductor chip comprising a first semiconductor substrate, first semiconductor devices located over a front side surface of the first semiconductor substrate, first through-substrate via structures vertically extending from the front side surface of the first semiconductor substrate to a backside surface of the first semiconductor substrate and are electrically isolated from the first semiconductor substrate by a respective tubular insulating spacer and by a backside insulating layer contacting the backside surface of the first semiconductor substrate, first backside bonding pad structures located on the first through-substrate via structures at a backside of the first semiconductor substrate, and first front side bonding pad structures electrically connected to the first integrated through-substrate via and pad structures, wherein the first semiconductor devices comprise a three-dimensional memory device including an alternating stack of insulating layers and electrically conductive layers and a two-dimensional array of memory stack structures including a respective vertical stack of memory elements located at levels of the electrically conductive layers;
• providing a second semiconductor chip comprising a second semiconductor substrate, second semiconductor devices located over a front side surface of the second semiconductor substrate, and second bonding pad structures electrically connected to a respective one of the second semiconductor devices, wherein the second semiconductor devices in the second semiconductor chip comprise peripheral devices that provide control signals for operation of the three-dimensional memory device of the first semiconductor chip;
• bonding the first backside bonding pad structures to a respective one of the second bonding pad structures by surface activated bonding;
• providing a third semiconductor chip comprising a third semiconductor substrate, third semiconductor devices located over a front side surface of the third semiconductor substrate, and third-chip bonding pad structures electrically connected to a respective one of the third semiconductor devices;
• bonding the first front side bonding pad structures on the first semiconductor chip to a respective one of the third-chip bonding pad structures by surface activated bonding;
• bonding an interposer by solder ball bonding to a topmost semiconductor chip in an assembly including the first, second, and third semiconductor chips, wherein the topmost semiconductor chip is selected from the third semiconductor chip or a topmost one of at least one additional semiconductor chip bonded to the third semiconductor chip by copper-to-copper bonding;
• and
• attaching a packaging substrate to the interposer, wherein bonding pads of the packaging substrate are electrically connected to second bonding pads of the interposer by wire bonding.