Circuitry and method for performing division

A data processing apparatus comprising:

• receiver circuitry to receive a signal corresponding to a divide instruction that identifies a dividend x and a divisor d;
• processing circuitry to perform, in response to said divide instruction, a radix-N division algorithm for a plurality of radix-N iterations to generate a result value q=x/d, where N is an integer power of 2, said integer power being greater than 1, each of said plurality of radix-N iterations being performed by:
• quotient digit calculation circuitry to determine a quotient value of that iteration q[i+1]based on a remainder value of a previous iteration rem[i], wherein the quotient value of that iteration q[i+1] comprises log2(N) bits and is within the range [−N/2,+N/2];
• and
• remainder calculation circuitry to determine a remainder value of that iteration rem[i+1]based on said quotient value of that iteration q[i+1] and said remainder value of said previous iteration rem[i];
• and
• result calculation circuitry to derive said result value q based on each quotient value determined by said quotient digit selection circuitry for each of said plurality of radix-N iterations, wherein
• for at least some of said plurality of radix-N iterations, said quotient digit calculation circuitry is adapted to speculatively determine a set of candidate values before a quotient value of said previous iteration is known and, in response to said quotient value of said previous iteration becoming known, determines said quotient value of that iteration q[i+1] based on one of said candidate values.