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US 10,353,670 B2Granted
Floating point unit with support for variable length numbers
AssigneeOracle International Corporation
InventorsJeffrey S. Brooks, Christopher H. Olson, Hesam Fathi Moghadam, Josephus C. Ebergen
Life of this patent
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Abstract
Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.
Claims19
A processor, comprising:
- a conversion circuit configured to:
- receive an indication of an operation, a first operand including a first plurality of mantissa digits, and a second operand including a second plurality of mantissa digits;
- convert an encoding of the first plurality of mantissa digits and the second plurality of mantissa digits from a machine-independent format to a binary coded centimal format;
- in response to a determination that the operation is a multiplication or division operation convert the encoding of the first plurality of mantissa digits and the second plurality of mantissa digits from the binary coded centimal format to a binary coded decimal format;
- and
- a multiplication circuit configured to perform the operation using the first operand and the second operand to generate an initial result, wherein the initial result includes a third plurality of mantissa digits encoded with the binary coded decimal format;
- and
- wherein the conversion circuit is further configured to convert an encoding of the third plurality of mantissa digits from the binary coded decimal format to the binary coded centimal format;
- and
- an adder circuit configured to perform, after the conversion circuit has converted the third plurality of mantissa digits to binary coded centimal format, a last operation of either the multiplication or the division operation using the initial result to generate a final result that includes a fourth plurality of mantissa digits encoded with the binary coded centimal format.
7 more elements
A method, comprising:
- receiving, by a conversion circuit included in a processor, information indicative of an operation, a first number, and a second number, wherein the first number and the second number are included in a database, and wherein the first number and the second number are encoded using a machine-independent format;
- converting, by the conversion circuit, an encoding of the first number and an encoding of the second number from the machine-independent format to a binary coded centimal format compatible with the processor;
- in response to determining that the operation is a multiplication or division operation:
- converting, by the conversion circuit, the encoding of the first number and the second number from the binary coded centimal format compatible with the processor to a binary coded decimal format compatible with the processor;
- performing, by the conversion circuit, the operation using the first number encoded with the binary coded decimal format compatible with the processor and the second number encoded with the binary coded decimal format compatible with the processor to generate an initial result encoded with the binary coded decimal format compatible with the processor;
- and
- converting, by the conversion circuit, an encoding of the initial result from the binary coded decimal format compatible with the processor to the binary coded centimal format compatible with the processor;
- and
- performing, after converting the encoded of the initial result, a last operation of either the multiplication or division operation using the initial result to generate a final result encoded with the binary coded centimal format.
6 more elements
A processor, comprising:
- an arithmetic logic unit comprising:
- a first circuit configured to process operands encoded in a binary coded centimal format;
- and
- a second circuit configured to perform multiplication and division operations on operands encoded in a binary coded decimal format;
- a conversion circuit configured, in response to receiving an indication of an arithmetic operation having first and second floating-point values encoded in a machine-independent format, to convert mantissa values of the first and second floating-point values to an encoding using the binary coded centimal format;
- wherein the conversion circuit, in response to determining that the arithmetic operation is a multiplication or division operation, is further configured to convert the encoding of the first and second floating-point values from the binary coded centimal format to the binary coded decimal format;
- and
- wherein the conversion circuit is further configured to convert an encoding of an initial result of the arithmetic operation performed by the second circuit on the first and second floating-point values from the binary coded decimal format to the binary coded centimal format;
- and
- wherein the first circuit is further configured to perform, after the conversion circuit has converted the encoding of the initial result to binary coded centimal format, a last operation of either the multiplication or the division operation using the initial result to generate a final result encoded with the binary coded centimal format.
7 more elements
Dependencies are inferred from the claim text.