Asymmetric chip-to-chip interconnect

A method comprising:

• transferring first data at a first rate from a first device operating at a first frequency to a second device operating at a second frequency, the first data comprising true data to be transferred in parallel along a first channel;
• transferring second data from the second device to the first device at a second rate different from the first rate, the second data comprising true data and corresponding complementary data along the first channel and a second channel, respectively;
• transferring the true data of the second data along at least one of a third channel and a fourth channel with corresponding complementary data being transferred in parallel along the other of the third channel and the fourth channel that is not transferring the true data;
• and
• receiving a data bit and its complement on the first channel and the second channel, respectively, by at least one differential receiver at the first device.

A memory controller, comprising:

• a first terminal and a second terminal;
• a first receiver including an input coupled to the first terminal, the first receiver configured to operate at a first frequency and to transfer data at a first rate and receive data at a second rate, the first rate being different from the second rate, the first receiver including at least one differential receiver to receive a data bit and its complement on the first channel and the second channel, respectively;
• a second receiver including an input coupled to the second terminal;
• a transmitter including a first output coupled to the first terminal and a second output coupled to the second terminal;
• and
• a multiplexer to receive first data having non-complementary data and complementary data and second data having non-complementary and complementary data and configured to send the first data and the second data to the transmitter;
• wherein each of the first receiver and the second receiver is to be operated at a first clock frequency and the multiplexer is to be operated at a second clock frequency different from the first clock frequency.