Modulators
AssigneeCirrus Logic, Inc.
InventorJohn Paul Lesso
Life of this patent
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Abstract
This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal (SIN) and outputs a time encoded signal (SPWM). A comparator (101) is located within a forward signal path of a feedback loop of the TEM. Also in the feedback loop are a filter (104) and a delay element (106) for applying a controlled delay. In some embodiments a latching element (101, 302; 106, 402) is located within the forward signal path to synchronize any signal transitions output from the latching element to a received first clock signal. Any signal transitions in the output (SOUT) from the modulator are thus synchronized to the first clock signal. In some embodiments the delay element (106) is a digital delay element which is synchronized to the first clock signal.
Claims24
A time-encoding modulator comprising:
- a forward signal path from a modulator input for receiving an input signal and a modulator output for outputting a time encoded signal;
- a feedback path forming a feedback loop with at least part of the forward signal path;
- a comparator located in the forward signal path within the feedback loop;
- a filter located within the feedback loop;
- a delay element for applying a controlled delay within the feedback loop;
- and
- a latching element within the forward signal path, the latching element being configured to receive a first clock signal and to synchronise any signal transitions output from the latching element to the first clock signal such that any signal transitions in the output from the modulator are synchronised to the first clock signal;
- wherein the delay element comprises a digital delay element which is synchronised to the first clock signal.
A time-encoding modulator for receiving an input signal and outputting a time encoded signal comprising:
- a comparator and a filter arranged in a feedback loop of the modulator to generate the time encoded signal based on the input signal;
- and
- at least one delay element for applying a controlled delay within the feedback loop,
- wherein the delay element is a digital element clocked by a first clock signal.
Dependencies are inferred from the claim text.