Data distribution fabric in scalable GPUs
AssigneeIntel Corporation
InventorsAltug Koker, Lakshminarayanan Striramassarma, Akif Ali
Life of this patent
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Abstract
In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies.
Claims20
A heterogeneous three-dimensional circuit stack comprising:
- a central processing unit (CPU);
- a graphics processing unit (GPU) stacked with the CPU, the GPU communicatively coupled with the CPU through one or more through-silicon-vias (TSVs);
- and
- a fabric interconnect including interconnect logic to communicatively couple the CPU and the GPU with a shared resource, wherein the interconnect logic is to enable coherent access to the shared resource for execution threads of the GPU, wherein to enable coherent access to the shared resource, the interconnect logic is to route traffic that originates from a single execution thread of the GPU within a single traffic class.
A method of interconnecting a heterogeneous three-dimensional circuit stack, the method comprising:
- communicatively coupling a central processing unit (CPU) to a graphics processing unit (GPU) through one or more through-silicon-vias (TSVs), the CPU vertically stacked with the GPU in the heterogeneous three-dimensional circuit stack, the CPU and the GPU communicatively coupled to a shared resource via a fabric interconnect, the CPU and the GPU coupled with the fabric interconnect via corresponding on-chip interconnects in each of the CPU and the GPU, and the fabric interconnect includes interconnect logic to enable coherent access to the shared resource;
- and
- enabling coherent access to the shared resource for execution threads of the GPU via programmatically pre-assigned traffic classifications, wherein coherent access to the shared resource is enabled by routing traffic originating from a single execution thread of the GPU within a single traffic class.
A system comprising:
- a heterogeneous three-dimensional circuit stack including a central processing unit (CPU) vertically stacked and communicatively coupled with a graphics processing unit (GPU) through one or more through-silicon-vias (TSVs);
- and
- a fabric interconnect including interconnect logic to communicatively couple the CPU and the GPU with a shared resource, wherein the interconnect logic is to enable coherent access to the shared resource for execution threads of the GPU, wherein to enable coherent access to the shared resource, the interconnect logic is to route traffic that originates from a single execution thread of the GPU within a single traffic class.
Dependencies are inferred from the claim text.