Method and apparatus for per-deck erase verify and dynamic inhibit in 3d NAND

A method comprising:

• during an erase sequence:
• performing an erase operation on a first memory deck and a second memory deck simultaneously, the first memory deck comprising a first plurality of wordlines and a first channel, the first memory deck comprising a first plurality of memory cells that are each coupled to the first channel and a respective one of the first plurality of wordlines, the second memory deck comprising a second plurality of wordlines and a second channel, the second channel coupled to the first channel, the second memory deck comprising a second plurality of memory cells that are each coupled to the second channel and a respective one of the second plurality of wordlines;
• after performing the erase operation on the first memory deck and the second memory deck simultaneously, determining an erase state of the first memory deck independently from an erase state of the second memory deck and determining an erase state of the second memory deck independently from an erase state of the first memory deck, wherein the determination of the erase state of the first memory deck is based on a first erase verify operation performed on the first memory deck and the determination of the erase state of the second memory deck is based on a second erase verify operation performed on the second memory deck;
• and
• inhibiting the second memory deck and performing an erase operation on the first memory deck based on a determination that the first memory deck is not in an erased state and the second memory deck is in an erased state.

At least one machine readable storage medium having instructions stored thereon, the instructions when executed by a machine to cause the machine to:

• during an erase sequence:
• perform an erase operation on a first memory deck and a second memory deck simultaneously, the first memory deck comprising a first plurality of wordlines and a first channel, the first memory deck comprising a first plurality of memory cells that are each coupled to the first channel and a respective one of the first plurality of wordlines, the second memory deck comprising a second plurality of wordlines and a second channel, the second channel coupled to the first channel, the second memory deck comprising a second plurality of memory cells that are each coupled to the second channel and a respective one of the second plurality of wordlines;
• after performing the erase operation on the first memory deck and the second memory deck simultaneously, determine an erase state of the first memory deck independently from an erase state of the second memory deck and determine an erase state of the second memory deck independently from an erase state of the first memory deck, wherein the determination of the erase state of the first memory deck is based on a first erase verify operation performed on the first memory deck and the determination of the erase state of the second memory deck is based on a second erase verify operation performed on the second memory deck;
• and
• inhibit the second memory deck and perform an erase operation on the first memory deck based on a determination that the first memory deck is not in an erased state and the second memory deck is in an erased state.

An apparatus comprising:

• a first memory deck comprising a first plurality of wordlines and a first channel, the first memory deck comprising a first plurality of memory cells that are each coupled to the first channel and a respective one of the first plurality of wordlines;
• a second memory deck comprising a second plurality of wordlines and a second channel, the second channel coupled to the first channel, the second memory deck comprising a second plurality of memory cells that are each coupled tothe second channel and a respective one of the second plurality of wordlines;
• wherein, during an erase sequence:
• an erase operation is to be performed on the first memory deck and the second memory deck simultaneously;
• after the erase operation is performed on the first memory deck and the second memory deck simultaneously, an erase state of the first memory deck is to be determined independently from an erase state of the second memory deck and an erase state of the second memory deck is to be determined independently from an erase state of the first memory deck, wherein the determination of the erase state of the first memory deck is based on a first erase verify operation performed on the first memory deck and the determination of the erase state of the second memory deck is based on a second erase verify operation performed on the second memory deck;
• the second memory deck is to be inhibited while an erase operation is performed on the first memory deck based on a determination that the first memory deck is not in an erased state and the second memory deck is in an erased state.