Multiplying delay locked loops with compensation for realignment error

An electronic system comprising:

• a multiplying delay locked loop (MDLL) configured to generate an output clock signal based on timing of a reference clock signal, wherein the MDLL comprises:
• a multiplexed oscillator configured to generate an oscillator signal, wherein the multiplexed oscillator includes a multiplexer configured to receive the reference clock signal and the oscillator signal;
• and
• an integrate and subtract circuit configured to compensate for a realignment error of the multiplexed oscillator based on a difference between a first integral of the oscillator signal and a second integral of the oscillator signal;
• and
• a downstream circuit having timing controlled by the output clock signal of the MDLL.

A method of compensating for realignment error in a multiplying delay locked loop (MDLL), the method comprising:

• generating an oscillator signal using a multiplexed oscillator, including regularly injecting a reference clock signal into the multiplexed oscillator to thereby provide phase realignment;
• determining a first integral of the oscillator signal;
• determining a second integral of the oscillator signal;
• and
• compensating for a realignment error of the multiplexed oscillator based on a difference between the first integral and the second integral.