US 10,340,445 B2 · PSTTM device with bottom electrode interface material

Abstract

MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include one or more electrode interface material layers disposed between a an electrode metal, such as TiN, and a seed layer of an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. The electrode interface material layers may include either or both of a Ta material layer or CoFeB material layer. In some Ta embodiments, a Ru material layer may be deposited on a TiN electrode surface, followed by the Ta material layer. In some CoFeB embodiments, a CoFeB material layer may be deposited directly on a TiN electrode surface, or a Ta material layer may be deposited on the TiN electrode surface, followed by the CoFeB material layer.

Claims16

Dependent claims

A magnetic tunneling junction (MTJ) material layer stack over a substrate, the stack comprising:

one or more electrode interface material layers comprising Ta or CoFeB over a first electrode metal;
a seed layer comprising Pt over the electrode interface material layers;
a synthetic antiferromagnet (SAF) stack over the seed layer;
a fixed magnetic material layer between the SAF and a free magnetic material layer;
and
a dielectric material layer between the fixed magnetic material layer and the free magnetic material layer.

3 more elements

A non-volatile memory device, comprising:

a first electrode;
a second electrode coupled to first interconnect metallization of the memory array;
a MTJ material stack between the first and second electrodes, wherein the MTJ material stack further comprises:
one or more electrode interface material layers comprising Ta or a CoFeB material over a first electrode metal;
a seed layer comprising Pt disposed over the one or more electrode interface material layers;
a synthetic antiferromagnet (SAF) stack over the seed layer;
a fixed magnetic material layer between the SAF and a free magnetic material layer;
and
a dielectric material layer between the fixed magnetic material layer and the free magnetic material layer;
and
a transistor with a first terminal electrically coupled to the first electrode, a second terminal electrically coupled to a second interconnect metallization of the memory array, and a third terminal electrically coupled to a third interconnect metallization of the memory array.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/755,446Filed 25 Sep 2015

Published

US 2018/0248115 A130 Aug 2018

Granted

2 Jul 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10N 50/10
Galvanomagnetic devices: magnetoresistive devices
G11C 11/161
Using elements in which the storage effect is based on magnetic spin effect: details concerning the memory cell structure, e.g. the layers of the…
H01F 10/30
Characterised by the substrate or intermediate layers: characterised by the composition of the intermediate layers , e.g. seed, buffer, template,…
H01F 10/3254
Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer: the spacer…

PSTTM device with bottom electrode interface material

Life of this patent

PSTTM device with bottom electrode interface material

Life of this patent

Abstract

Claims16