US 10,332,597 B2 · Floating gate OTP/MTP structure and method for producing the same

Abstract

A method of forming a FG OTP/MTP cell with a P+ drain junction at the NCAP region and the resulting device are provided. Embodiments include forming MVPW regions laterally separated in a p-sub; forming a MVNW region in the p-sub between the MVPW regions; forming a first RX, a second RX, and a third RX in the MVPW and MVNW regions, respectively; forming a first and a second pair of floating gates separated over and perpendicular to the first and second RX and the second and third RX, respectively; forming a N+ source region between and adjacent to each FG of the first and the second pair in the second RX; and forming a pair of P+ drain regions in the second RX, each P+ drain region adjacent to a FG of the first pair and a FG of the second pair and remote from the N+ source region.

Claims20

Dependent claims

A method comprising:

forming a first middle-voltage p-type well (MVPW) region and a second MVPW region laterally separated in a p-type substrate (p-sub);
forming a middle-voltage n-type well (MVNW) region in the p-sub between and adjacent to the first MVPW region and the second MVPW region;
forming a first active region (RX), a second RX, and a third RX in the first MVPW region, the MVNW region, and the second MVPW region, respectively;
forming a first pair of floating gates and a second pair of floating gates laterally separated over and perpendicular to the first RX and the second RX and the second RX and the third RX, respectively;
forming a n-type (N+) source region between and adjacent to each floating gate (FG) of the first pair and the second pair in the second RX;
and
forming a pair of p-type (P+) drain regions in the second RX, each P+ drain region adjacent to a FG of the first pair and a FG of the second pair and remote from the N+ source region.

4 more elements

A device comprising:

a first middle-voltage p-type well (MVPW) region and a second MVPW region in a p-type substrate (p-sub);
a middle-voltage n-type well (MVNW) region in the p-sub between and adjacent to the first MVPW region and the second MVPW region;
a first active region (RX), a second RX, and a third RX in the first MVPW region, the MVNW region, and the second MVPW region, respectively;
a first pair of floating gates and a second pair of floating gates laterally separated and over and perpendicular to the first RX and the second RX and the second RX and the third RX, respectively;
a first n-type (N+) source region between and adjacent to each floating gate (FG) in the second RX;
a pair of p-type (P+) boron (B) or B plus difluoroboron (B+BF2) drain regions in the second RX, each P+B or B+BF2 source region adjacent to a FG of the first pair and a FG of the second pair and remote from the N+ source region;
a first N+ drain region and a second N+ drain region on opposite sides of the first pair of floating gates in the first RX;
a third N+ drain region and a fourth N+ drain region on opposite sides of the second pair of floating gates in the second RX;
a second N+ source region between the first pair of floating gates in the first RX;
and
a third N+ source region between the second pair of floating gates in the third RX.

8 more elements

Dependencies are inferred from the claim text.

Floating gate OTP/MTP structure and method for producing the same

Life of this patent

Floating gate OTP/MTP structure and method for producing the same

Life of this patent

Abstract

Claims20