Loading patent…
AssigneeNational Institute of Advanced Industrial Science and Technology
InventorKeiko Masumoto
Estimating the term…
A subject of present invention is to enable reducing, even in growth at a high C/Si ratio, contamination by different polytypes with respect to a silicon carbide epitaxial wafer having a low off-angle, and to provide the silicon carbide epitaxial wafer which enables forming a reliable high voltage silicon carbide semiconductor element. The silicon carbide epitaxial wafer of the present invention is a silicon carbide epitaxial wafer comprising an epitaxially grown layer disposed on a silicon carbide substrate having an α-type crystal structure and an off-angle tilted at an angle of more than 0° and less than 4° from a (0001) Si plane or a (000-1) C plane, wherein a region of a step bunching including five to ten bunched steps of 1 nm in height occupies 90% or more of the surface of the silicon carbide substrate.
A silicon carbide epitaxial wafer comprising an epitaxially grown layer disposed on a silicon carbide substrate having an α-type crystal structure and an off-angle tilted at an angle larger than 0° and 1° or less from a (0001) Si plane,
A silicon carbide epitaxial wafer comprising an epitaxially grown layer disposed on a silicon carbide substrate comprising an α-type crystal structure and an off-angle tilted at an angle larger than 0° and less than 4° from a (0001) Si plane or a (000-1) C plane,
A silicon carbide epitaxial wafer comprising:
Dependencies are inferred from the claim text.