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US 10,329,142 B2Granted
Wafer level package and method of manufacturing the same
AssigneeSamsung Electro-Mechanics Co., Ltd.
InventorsMoon Chul Lee, Duck Hwan Kim, Yeong Gyu Lee, Jae Chang Lee, Tae Yoon Kim, Kyong Bok Min
Life of this patent
Estimating the term…
Abstract
A wafer level package includes a wafer member having inner cavities in which circuit elements are disposed, element wall members disposed on an internal surface of the wafer member and enclosing element sections in which the circuit elements are disposed, and clearance wall members disposed on external surfaces of the element wall members and dividing a space between the element sections into clearance sections.
Claims18
A wafer level package comprising:
- a wafer member having inner cavities in which a circuit element is disposed;
- an element wall member extending vertically on an internal surface of the wafer member and enclosing an element section in which the circuit element is disposed, the element section spaced apart horizontally from an adjacent element section by a dicing space;
- and
- a clearance wall member extending horizontally from an external surface of the element section across the dicing space to an external surface of the adjacent element section to divide the dicing space between the element sections into clearance sections isolated each from the other.
1 more element
A wafer level package comprising:
- a first wafer and a second wafer with a vertical space therebetween;
- first wall members that allocate a portion of the vertical space as element sections, the element sections each comprising one or more circuit elements, and each element section spaced apart from an adjacent element section by a horizontal channel space between external surfaces of the first wall members;
- and
- second wall members, each extending from a first wall member across the horizontal channel space between adjacent element sections to an adjacent first wall member of the adjacent element section to divide a portion of the horizontal channel space external to the element sections into clearance sections isolated each from the other.
1 more element
A semiconductor device, comprising:
- a circuit element disposed on a device substrate;
- an element wall member extending vertically between the device substrate and a cap substrate and enclosing an element section in which the circuit element is disposed;
- and
- a clearance wall member extending horizontally from an external surface of the element wall member,
- wherein the clearance wall member comprises a portion protruding from the device substrate or the cap substrate.
2 more elements
Dependencies are inferred from the claim text.