Wide-range local oscillator (LO) generators and apparatuses including the same

An apparatus for wireless communication, the apparatus comprising:

• a local oscillator generator (LO generator) configured to generate a first internal oscillator signal based on an input oscillator signal, generate a second internal oscillator signal based on dividing a frequency of the first internal oscillator signal, and generate an LO signal based on the second internal oscillator signal, the LO generator further configured to receive a first power voltage;
• a mixer configured to receive the LO signal;
• and
• a controller configured to control the frequency of the input oscillator signal and a frequency division ratio of the LO generator based on a carrier frequency of the wireless communication, the controller further configured to control the first power voltage based on the frequency of the input oscillator signal and the frequency division ratio of the LO generator,
• wherein the LO generator includes a frequency dividing circuit configured to generate the second internal oscillator signal based on dividing the frequency of the first internal oscillator signal,
• wherein the frequency dividing circuit includes
• a plurality of first frequency dividers configured to mutually independently divide the frequency of the first internal oscillator signal and generate separate, respective output signals of a plurality of output signals, and
• a selection circuit configured to selectively output one output signal of the plurality of output signals of the plurality of first frequency dividers as the second internal oscillator signal,
• wherein the selection circuit includes at least one 2:1 multiplexer disposed in a hierarchical fashion.

A frequency divider configured to divide a frequency of an oscillator signal of an oscillator, the frequency divider comprising:

• an injection-locked oscillator, the injection-locked oscillator including a plurality of gated inverters, the injection-locked oscillator including a sequence of stages, each stage including at least two gated inverters of the plurality of gated inverters,
• wherein each gated inverter of the plurality of gated inverters includes first and second PMOS transistors and first and second NMOS transistors which are each a fin field-effect transistor (FinFET), the first and second PMOS transistors and the first and second NMOS transistors connected in series sequentially from a positive power voltage to a negative power voltage,
• wherein the frequency divider is configured to generate, in a given stage of the sequence of stages, an input signal of a next stage in a plurality of drains of the second PMOS transistor and the first NMOS transistor of a gate inverter of the given stage, respectively,
• wherein the frequency divider is configured to apply, in the given stage of the sequence of stages, an output signal of a previous stage to a plurality of gates of the first PMOS transistor and the second NMOS transistor of the gate inverter of the given stage, respectively, respectively,
• wherein the frequency divider is configured to apply the oscillator signal to a plurality of gates of the second PMOS transistor and the first NMOS transistor of the gate inverter of the given stage, respectively.