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US 10,326,417 B1Granted
Offset nulling for high-speed sense amplifier
AssigneeQUALCOMM Incorporated
InventorsTodd Morgan Rasmus, Minhan Chen
Life of this patent
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Abstract
A resistor in a pair of resistors is selectively coupled to a current source through a selection switch during the reset phase of a voltage-mode sense amplifier so that one evaluation node for the voltage-mode sense amplifier is discharged from a power supply voltage by an ohmic voltage drop across the selectively-coupled resistor to null an offset for the voltage-mode sense amplifier.
Claims20
A voltage-mode sense amplifier, comprising:
- a differential pair of transistors;
- a pair of evaluation nodes, wherein the differential pair of transistors are configured to discharge, during an evaluation phase, one of the evaluation nodes faster than a remaining one of the evaluation nodes responsive to a binary value for a differential input signal;
- a current source;
- a pair of resistors corresponding to the pair of evaluation nodes on a one-to-one basis, wherein each resistor has a first terminal coupled to a power supply node and has a second terminal coupled to the corresponding evaluation node;
- a pair of switch transistors corresponding to the pair of resistors on a one-to-one basis, wherein each switch transistor is coupled between the second terminal of the corresponding resistor and the corresponding evaluation node, and wherein each switch transistor is configured to switch on during a reset phase and to switch off during the evaluation phase;
- and
- a selection switch configured to couple the current source to the second terminal of a selected one of the resistors to produce an ohmic voltage drop at the second terminal of the selected one of the resistors.
4 more elements
A method of evaluating a differential data input signal in a voltage-mode sense amplifier, comprising:
- during a reset phase, charging a first evaluation node to a power supply voltage while charging a second evaluation node to the power supply voltage minus an ohmic voltage drop resulting from a current conducted through a resistor;
- during an evaluation phase following the reset phase, driving a differential pair of transistors with a differential input signal to discharge either the first evaluation node or the second evaluation node faster than a remaining one of the first evaluation node and the second evaluation node to produce an evaluation phase voltage difference between the first evaluation node and the second evaluation node responsive to a binary value for the differential input signal;
- and
- latching an output signal responsive to the voltage difference between the first evaluation node and the second evaluation node, wherein the voltage drop resulting from the current conducted through the resistor nulls an offset for the voltage-mode sense amplifier.
1 more element
A voltage-mode sense amplifier, comprising:
- a differential pair of transistors;
- a pair of evaluation nodes, wherein the differential pair of transistors are configured to discharge, during an evaluation phase, one of the evaluation node faster than a remaining one of the evaluation nodes responsive to a binary value for a differential input signal;
- a latch configured to latch a binary state for a data output signal during the evaluation phase responsive to a voltage difference between the pair of evaluation nodes;
- and
- means for charging a first evaluation node in the pair of evaluation nodes to a power supply voltage during a reset phase and to charge a second evaluation node in the pair of evaluation nodes to the power supply voltage minus an ohmic voltage drop during the reset phase.
2 more elements
Dependencies are inferred from the claim text.